wireguard-linux/drivers/pinctrl/nuvoton, branch stable

Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2026-08-24T15:46:03Z

Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ...

pinctrl: Use IRQ trigger mask helpers

2026-08-06T21:40:54Z

Use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH instead of open-coded trigger type combinations in irqchip callbacks. No functional change intended. Assisted-by: Claude:claude-sonnet-5 Signed-off-by: Maulik Shah Acked-by: Viresh Kumar Signed-off-by: Linus Walleij

pinctrl: npcm8xx: fix debounce register selection

2026-07-24T21:33:01Z

Each DBNCS register programs debounce source selection for 16 GPIOs. The current offset calculation advances the register address every four GPIOs, so offsets 4-15 and 20-31 end up touching the wrong selector register. Advance the DBNCS offset per 16 GPIOs so each line uses the debounce selector bank that matches the hardware layout. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij

pinctrl: npcm8xx: correct JM1 and SMB7 pin flags

2026-07-24T21:33:01Z

Pins 136-140 and 142 are currently advertised as having both drive- strength and slew-rate controls, while pins 141 and 143 expose no slew control at all. According to the hardware description, those pins only support slew-rate configuration. Update the pin flags accordingly so pinconf exposes the capabilities that the hardware actually implements. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij

pinctrl: npcm8xx: move GPIO IRQ setup into request_resources

2026-07-24T21:33:01Z

npcmgpio_irq_startup() calls pinctrl_gpio_direction_input(), which may sleep while taking the pinctrl core mutex. That makes IRQ startup trip lockdep when CONFIG_PROVE_LOCKING is enabled. Move the direction change into irq_request_resources() and keep startup limited to the ack and unmask operations that are safe in atomic context. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij

pinctrl: npcm8xx: rename GPIO7 IOX2 signal to DO

2026-07-24T21:33:00Z

The pin description for GPIO7 spells the IOX2 output signal as D0. The datasheet names that signal IOX2_DO, matching the rest of the IOX naming scheme. Rename the pin description accordingly. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij

pinctrl: npcm8xx: clear pending GPIO events during init

2026-07-24T21:33:00Z

A bank may retain pending event status across resets of the GPIO block. If probe leaves the old state in place, the chained IRQ handler can see spurious events as soon as the irqchip is registered. Disable event generation and clear EVST before wiring each GPIO bank into gpiolib so the driver starts from a known state. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij

pinctrl: npcm8xx: support RG2 drive strength selection

2026-07-24T21:33:00Z

RG2 pins 110-113 and 208-209 do not use the per-bank ODSC bit that the driver relies on for the rest of the drive-strength handling. Their strength is encoded in GCR_DSCNT[7:6] and supports four values: 8, 12, 16 and 24mA. Mark those pins as a dedicated drive-strength class and translate the pinconf get/set operations to the shared GCR_DSCNT field so the full hardware range becomes available. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij

pinctrl: npcm8xx: enable RMII outputs from RMII groups

2026-07-24T21:33:00Z

NPCM8xx uses GCR_INTCR4 bits to release the R1, R2 and RMII3 transmit outputs from Hi-Z. Those bits need to follow the mandatory r1, r2 and rmii3 pin groups. The R1_OEn, R2_OEn and R3_OEn side groups are optional and should not be required just to enable RMII transmit outputs. Program the INTCR4 bits when the corresponding RMII groups are selected and clear them again when those pins switch back to GPIO or another shared function. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij

pinctrl: npcm8xx: drop RTS/CTS pins from bmcuart1

2026-07-24T21:33:00Z

The bmcuart1 group currently claims BU1_RTS and BU1_CTS in addition to TXD and RXD. That prevents boards from using the modem-control pins independently through the dedicated nbu1crts function. Limit bmcuart1 to the TXD/RXD pair and let users opt into BU1_RTS and BU1_CTS explicitly through the nbu1crts group when those signals are needed. Signed-off-by: Tomer Maimon Signed-off-by: Linus Walleij