wireguard-linux/drivers/pinctrl/samsung, branch update-toolchain

pinctrl: samsung: drop redundant drvdata assignment

2024-04-30T07:41:58Z

Fix W=1 warning: drivers/pinctrl/samsung/pinctrl-samsung.c: In function ‘samsung_gpio_set_direction’: drivers/pinctrl/samsung/pinctrl-samsung.c:633:42: warning: variable ‘drvdata’ set but not used [-Wunused-but-set-variable] Fixes: f9c744747973 ("pinctrl: samsung: support a bus clock") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202404300825.6lxLwvUY-lkp@intel.com/ Reviewed-by: André Draszik Link: https://lore.kernel.org/r/20240430060304.12332-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski

pinctrl: samsung: support a bus clock

2024-04-29T17:19:30Z

On some Samsung-based SoCs there are separate bus clocks / gates each for each pinctrl instance. To be able to access each pinctrl instance's registers, this bus clock needs to be running, otherwise register access will hang. Google Tensor gs101 is one example for such an implementation. Update the driver to handle this optional bus clock: * handle an optional bus clock from DT * prepare it during driver probe * enclose all relevant register accesses with a clock enable & disable Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240426-samsung-pinctrl-busclock-v3-2-adb8664b8a7e@linaro.org Signed-off-by: Krzysztof Kozlowski

pinctrl: samsung: constify iomem pointers

2023-12-28T21:13:17Z

Constify few pointers to iomem, where the destination memory is not modified, for code safety and readability. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20231223191902.22857-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij

pinctrl: samsung: add exynosautov920 pinctrl

2023-12-13T07:49:33Z

Add pinctrl data for ExynosAutov920 SoC. It has a newly applied pinctrl register layer for ExynosAuto series. Pinctrl data for ExynosAutoV920 SoC. - GPA0,GPA1 (10): External wake up interrupt - GPQ0 (2): SPMI (PMIC I/F) - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231211114145.106255-3-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski

pinctrl: samsung: support ExynosAuto GPIO structure

2023-12-13T07:42:38Z

New ExynosAuto series GPIO have a different register structure. In the existing Exynos series, EINT control register is enumerated after a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET, EXYNOS_GPIO_EMASK_OFFSET). However, from ExynosAutov920 SoC, the register that controls EINT belongs to each GPIO bank, and each GPIO bank has 0x1000 align. This is a structure to protect the GPIO bank using S2MPU in VM environment, and will only be applied in ExynosAuto series SoCs. -------------------------------------------------------------- | Original Exynos | ExynosAuto | |------------------------------------------------------------| | 0x0 GPIO_CON | 0x0 GPIO_CON | | 0x4 GPIO_DAT | 0x4 GPIO_DAT | | 0x8 GPIO_PUD | 0x8 GPIO_PUD | | 0xc GPIO_DRV | 0xc GPIO_DRV | | 0x10 GPIO_CONPDN | 0x10 GPIO_CONPDN | | 0x14 GPIO_PUDPDN | 0x14 GPIO_PUDPDN | |----------------------------| 0x18 EINT_CON (per_bank) | | ... | 0x1c EINT_FLTCON0 (per_bank) | | ... | 0x20 EINT_FLTCON1 (per_bank) | | ... | 0x24 EINT_MASK (per_bank) | | ... | 0x28 EINT_PEND (per_bank) | |----------------------------|-------------------------------| | 0x700 EINT_CON (global) | ... | | 0x800 EINT_FLTCON (global) | ... | | 0x900 EINT_MASK (global) | ... | | 0xa00 EINT_FEND (global) | ... | -------------------------------------------------------------- Signed-off-by: Jaewon Kim Link: https://lore.kernel.org/r/20231211114145.106255-2-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski

pinctrl: samsung: Add gs101 SoC pinctrl configuration

2023-12-12T19:15:27Z

Add support for the pin-controller found on the gs101 SoC used in Pixel 6 phones. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20231211162331.435900-10-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski

pinctrl: samsung: add irq_set_affinity() for non wake up external gpio interrupt

2023-11-30T07:53:03Z

To support affinity setting for non wake up external gpio interrupt, add irq_set_affinity callback using irq number from pinctrl driver data. Before this patch, changing the irq affinity of gpio interrupt is not possible: # cat /proc/irq/418/smp_affinity 3ff # echo 00f > /proc/irq/418/smp_affinity # cat /proc/irq/418/smp_affinity 3ff # cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 ... 418: 3631 0 0 0 ... With this patch applied, it's possible to change irq affinity of gpio interrupt: # cat /proc/irq/418/smp_affinity 3ff # echo 00f > /proc/irq/418/smp_affinity # cat /proc/irq/418/smp_affinity 00f # cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 ... 418: 3893 201 181 188 ... Signed-off-by: Youngmin Nam Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Link: https://lore.kernel.org/r/20231126094618.2545116-1-youngmin.nam@samsung.com Signed-off-by: Krzysztof Kozlowski

pinctrl: samsung: do not offset pinctrl numberspaces

2023-10-09T10:37:21Z

Past versions of this driver have manually calculated base values for both the pinctrl numberspace and the global GPIO numberspace, giving both the same values. This was necessary for the global GPIO numberspace, since its values need to be unique system-wide. However, it was not necessary for the pinctrl numberspace, since its values only need to be unique for a single instance of the pinctrl device. It was just convenient to use the same values for both spaces. Right now those calculations are only used for the pinctrl numberspace, since GPIO numberspace bases are selected by the GPIO subsystem. Therefore, those calculations are unnecessary. Signed-off-by: Mateusz Majewski Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20231006125557.212681-5-m.majewski2@samsung.com Signed-off-by: Krzysztof Kozlowski

pinctrl: samsung: choose GPIO numberspace base dynamically

2023-10-09T10:37:21Z

Selecting it statically is deprecated and results in a warning while booting the system: gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation. Signed-off-by: Mateusz Majewski Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20231006125557.212681-4-m.majewski2@samsung.com Signed-off-by: Krzysztof Kozlowski

pinctrl: samsung: use add_pin_ranges method to add pinctrl ranges

2023-10-09T10:37:21Z

This is preferable since we can read the base in the global GPIO numberspace from the chip instead of needing to select it ourselves. Past versions could not do this, since they needed to add all the ranges before enabling the pinctrl subsystem, which was done before registering the GPIO chip. However, right now we enable the pinctrl subsystem after registering the chip and so this became possible. Signed-off-by: Mateusz Majewski Reviewed-by: Sam Protsenko Tested-by: Sam Protsenko Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20231006125557.212681-3-m.majewski2@samsung.com Signed-off-by: Krzysztof Kozlowski