wireguard-linux/drivers/platform/x86/intel_speed_select_if, branch jd/unified-crypt-queue

Merge tag 'platform-drivers-x86-v5.7-1' of git://git.infradead.org/linux-platform-drivers-x86

2020-03-31T23:43:40Z

Pull x86 platform driver updates from Andy Shevchenko: - Fix for improper handling of fan_boost_mode in sysfs for ASUS laptops. - On newer ASUS laptops the 1st battery is named differently, here is a fix. - Fix Lex 2I385SW to allow both network cards to be used. - The power integrated circuit driver for Surface 3 has been added. - Refactor and clean up of Intel PMC driver and enable it on Intel Jasper Lake. - Clean up of Dell RBU driver. - Big update for Intel Speed Select technology support tool and driver. * tag 'platform-drivers-x86-v5.7-1' of git://git.infradead.org/linux-platform-drivers-x86: (75 commits) platform/x86: surface3_power: Fix always true condition in mshw0011_space_handler() platform/x86: surface3_power: Fix Kconfig section ordering platform/x86: surface3_power: Add missed headers platform/x86: surface3_power: Reformat GUID assignment platform/x86: surface3_power: Drop useless macro ACPI_PTR() platform/x86: surface3_power: Prefix POLL_INTERVAL with SURFACE_3 platform/x86: surface3_power: Simplify mshw0011_adp_psr() to one liner platform/x86: surface3_power: Use dev_err() instead of pr_err() platform/x86: surface3_power: Drop unused structure definition platform/x86: surface3_power: MSHW0011 rev-eng implementation platform/x86: intel_pmc_core: Make pmc_core_substate_res_show() generic platform/x86: intel_pmc_core: Make pmc_core_lpm_display() generic for platforms that support sub-states tools/power/x86/intel-speed-select: Fix a typo in error message tools/power/x86/intel-speed-select: Update version tools/power/x86/intel-speed-select: Avoid duplicate Package strings for json tools/power/x86/intel-speed-select: Add display for enabled cpus count tools/power/x86/intel-speed-select: Print friendly warning for bad command line tools/power/x86/intel-speed-select: Fix avx options for turbo-freq feature tools/power/x86/intel-speed-select: Improve CLX commands tools/power/x86/intel-speed-select: Show error for invalid CPUs in the options ...

platform/x86: Convert to new CPU match macros

2020-03-24T20:33:00Z

The new macro set has a consistent namespace and uses C99 initializers instead of the grufty C89 ones. Get rid the of the local macro wrappers for consistency. Signed-off-by: Thomas Gleixner Signed-off-by: Borislav Petkov Reviewed-by: Andy Shevchenko Reviewed-by: Greg Kroah-Hartman Link: https://lkml.kernel.org/r/20200320131509.766573641@linutronix.de

platform/x86: ISST: Fix wrong unregister type

2020-03-20T12:44:47Z

The MMIO driver is not unregistering with the correct type with the ISST common core during module removal. This should be unregistered with ISST_IF_DEV_MMIO instead of ISST_IF_DEV_MBOX. Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko

platform/x86: ISST: Allow additional core-power mailbox commands

2020-01-20T09:39:31Z

To discover core-power capability, some new mailbox commands are added. Allow those commands to execute. Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko

platform/x86: ISST: Allow additional TRL MSRs

2019-09-09T10:19:35Z

Additional Turbo Ratio Limit (TRL) MSRs are required to get bucket vs core count relationship. So add them to the list of allowed MSRs. Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko

platform/x86: ISST: Use dev_get_drvdata

2019-07-30T11:12:51Z

Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan Signed-off-by: Andy Shevchenko

platform/x86: ISST: Restore state on resume

2019-07-02T15:41:16Z

Commands which causes PUNIT writes, store them and restore them on system resume. The driver stores all such requests in a hash table and stores the the latest mailbox request parameters. On resume these commands mail box commands are executed again. There are only 5 such mail box commands which will trigger such processing so a very low overhead in store and execute on resume. Also there is no order requirement for mail box commands for these write/set commands. There is one MSR request for changing turbo ratio limits, this also stored and get restored on resume and cpu online. Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko

platform/x86: ISST: Add Intel Speed Select PUNIT MSR interface

2019-07-02T15:41:16Z

While using new non arhitectural features using PUNIT Mailbox and MMIO read/write interface, still there is need to operate using MSRs to control PUNIT. User space could have used user user-space MSR interface for this, but when user space MSR access is disabled, then it can't. Here only limited number of MSRs are allowed using this new interface. Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko

platform/x86: ISST: Add Intel Speed Select mailbox interface via MSRs

2019-07-02T15:41:16Z

Add an IOCTL to send mailbox commands to PUNIT using PUNIT MSRs for mailbox. Some CPU models don't have PCI device, so need to use MSRs. A limited set of mailbox commands can be sent to PUNIT. This MMIO interface is used by the intel-speed-select tool under tools/x86/power to enumerate and control Intel Speed Select features. The MBOX commands ids and semantics of the message can be checked from the source code of the tool. Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko

platform/x86: ISST: Add Intel Speed Select mailbox interface via PCI

2019-07-02T15:41:16Z

Add an IOCTL to send mailbox commands to PUNIT using PUNIT PCI device. A limited set of mailbox commands can be sent to PUNIT. This MMIO interface is used by the intel-speed-select tool under tools/x86/power to enumerate and control Intel Speed Select features. The MBOX commands ids and semantics of the message can be checked from the source code of the tool. Signed-off-by: Srinivas Pandruvada Signed-off-by: Andy Shevchenko