wireguard-linux/drivers/platform, branch jd/orphan-parallel

Merge tag 'tag-chrome-platform-for-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux

2020-10-23T17:54:13Z

Pull chrome platform updates from Benson Leung: "cros-ec: - Error code cleanup across cros-ec by Guenter - Remove cros_ec_cmd_xfer in favor of cros_ec_cmd_xfer_status cros_ec_typec: - Landed initial USB4 support in typec connector class driver for cros_ec - Role switch bugfix on disconnect, and reordering configuration steps cros_ec_lightbar: - Fix buffer outsize and result for get_lightbar_version misc: - Remove config MFD_CROS_EC, now that transition from MFD is complete - Enable KEY_LEFTMETA in new location on arm based cros-ec-keyboard keymap" * tag 'tag-chrome-platform-for-v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux: ARM: dts: cros-ec-keyboard: Add alternate keymap for KEY_LEFTMETA platform/chrome: Use kobj_to_dev() instead of container_of() platform/chrome: cros_ec_proto: Drop cros_ec_cmd_xfer() platform/chrome: cros_ec_proto: Update cros_ec_cmd_xfer() call-sites platform/chrome: Kconfig: Remove the transitional MFD_CROS_EC config platform/chrome: cros_ec_lightbar: Reduce ligthbar get version command platform/chrome: cros_ec_trace: Add fields to command traces platform/chrome: cros_ec_typec: Re-order connector configuration steps platform/chrome: cros_ec_typec: Avoid setting usb role twice during disconnect platform/chrome: cros_ec_typec: Send enum values to usb_role_switch_set_role() platform/chrome: cros_ec_typec: USB4 support pwm: cros-ec: Simplify EC error handling platform/chrome: cros_ec_proto: Convert EC error codes to Linux error codes platform/input: cros_ec: Replace -ENOTSUPP with -ENOPROTOOPT pwm: cros-ec: Accept more error codes from cros_ec_cmd_xfer_status platform/chrome: cros_ec_sysfs: Report range of error codes from EC cros_ec_lightbar: Accept more error codes from cros_ec_cmd_xfer_status iio: cros_ec: Accept -EOPNOTSUPP as 'not supported' error code

Merge tag 'platform-drivers-x86-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86

2020-10-14T17:43:24Z

Pull x86 platform driver updates from Hans de Goede: "Rather calm cycle for x86 platform drivers, all these have been in for-next for a couple of days with no bot complaints. Highlights: - PMC TigerLake fixes and new RocketLake support - various small fixes / updates in other drivers/tools" * tag 'platform-drivers-x86-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: MAINTAINERS: update X86 PLATFORM DRIVERS entry with new kernel.org git repo platform/x86: mlx-platform: Add capability field to platform FAN description platform_data/mlxreg: Extend core platform structure platform_data/mlxreg: Update module license platform/x86: mlx-platform: Remove PSU EEPROM configuration MAINTAINERS: Update maintainers for pmc_core driver platform/x86: intel_pmc_core: fix: Replace dev_dbg macro with dev_info() platform/x86: intel_pmc_core: Add Intel RocketLake (RKL) support platform/x86: intel_pmc_core: Clean up: Remove the duplicate comments and reorganize platform/x86: intel_pmc_core: Fix the slp_s0 counter displayed value platform/x86: intel_pmc_core: Fix TigerLake power gating status map platform/x86: pmc_core: Use descriptive names for LPM registers tools/power/x86/intel-speed-select: Update version for v5.10 tools/power/x86/intel-speed-select: Fix missing base-freq core IDs platform/x86: hp-wmi: add support for thermal policy

platform/x86: mlx-platform: Add capability field to platform FAN description

2020-10-07T21:21:04Z

Set 'capability' field to FAN core platform data.. The content of 'capability' register allows to set the mapping between the drawers and tachometers. The motivation is to avoid adding a new code in the future in order to distinct between the systems types supporting a different kinds of the FAN drawers. Signed-off-by: Vadim Pasternak Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20200923172053.26296-6-vadimp@nvidia.com Signed-off-by: Hans de Goede

platform/x86: mlx-platform: Remove PSU EEPROM configuration

2020-10-07T21:20:48Z

Remove PSU EEPROM configuration for systems class equipped with Mellanox chip Spectrume-2. Till now all the systems from this class used few types of power units, all equipped with EEPROM device with address space two bytes. Thus, all these devices have been handled by EEPROM driver "24c32". There is a new requirement is to support power unit replacement by "off the shelf" device, matching electrical required parameters. Such device could be equipped with different EEPROM type, which could be one byte address space addressing or even could be not equipped with EEPROM. In such case "24c32" will not work. Fixes: 1bd42d94ccab ("platform/x86: mlx-platform: Add support for new 200G IB and Ethernet systems") Signed-off-by: Vadim Pasternak Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20200923172053.26296-2-vadimp@nvidia.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: fix: Replace dev_dbg macro with dev_info()

2020-10-07T21:07:38Z

dev_dbg macro is used to dump the debug registers in resume from an S0ix failure. However, when CONFIG_DYNAMIC_DEBUG is not set, the user may not be able to find the debug dump on an S0ix failure which defeats the purpose. The output of these messages is already controlled by a module parameter, warn_on_s0ix_failures, making it a 2 step process to enable anyway when CONFIG_DYNAMIC_DEBUG is set. Hence, replace dev_dbg with dev_info, allowing the control of the messages solely through the module parameter which is N by default. Fixes commit 913f984a8347 ("platform/x86: intel_pmc_core: Add an additional parameter to pmc_core_lpm_display()") Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20201007035108.31078-4-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Add Intel RocketLake (RKL) support

2020-10-07T21:07:38Z

Add RocketLake to the list of the platforms that intel_pmc_core driver supports for pmc_core device. RocketLake reuses all the TigerLake PCH IPs. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Cc: Tony Luck Cc: Rui Zhang Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20201007035108.31078-3-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Clean up: Remove the duplicate comments and reorganize

2020-10-07T21:07:29Z

Some of the Cannon Lake PCH IPs are reused by most of the platforms such as Ice Lake, Tiger Lake, Elkhart Lake, Jasper Lake and can be reused by future platforms as well. The same was mentioned via comments not once but twice in an array of bit map structs for Cannon Lake (cnp_pfear_map). Hence, remove the duplicate comments and reorganize them. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Cc: Tony Luck Cc: Rui Zhang Suggested-by: Dave Hansen Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20201007035108.31078-2-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Fix the slp_s0 counter displayed value

2020-10-07T21:06:29Z

slp_s0 counter value displayed via debugfs interface is calculated by multiplying the granularity for crystal oscillator tick as 100us with the value read from using slp_s0 offset. But the granularity of the tick varies from platform to platform and it needs to be fixed. Hence, specify granularity of the tick for each platform, so that the value of the slp_s0 counter is accurate. Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20201006224702.12697-4-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Fix TigerLake power gating status map

2020-10-07T21:06:24Z

TigerLake's LPM power gating status register has errors in the bit-to-name mapping as well as with the marked reserved bits according to the actual implementation. Hence, update the right bit-to-name mapping and the reserved bits in accordance with actual implementation. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20201006224702.12697-3-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: pmc_core: Use descriptive names for LPM registers

2020-10-07T21:05:53Z

TigerLake Lower Power Mode (LPM) registers are grouped by functionality but were given simple enumerated names in the code (lpm0, lpm1, ...). Instead, give the register blocks names that describe their usage. Suggested-by: Andy Shevchenko Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20201006224702.12697-2-david.e.box@linux.intel.com Signed-off-by: Hans de Goede