<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/ptp/Kconfig, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/ptp/Kconfig?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/ptp/Kconfig?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-03-06T01:25:07Z</updated>
<entry>
<title>ptp: add VMware virtual PTP clock driver</title>
<updated>2020-03-06T01:25:07Z</updated>
<author>
<name>Vivek Thampi</name>
<email>vithampi@vmware.com</email>
</author>
<published>2020-02-28T05:32:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7d10001e20e46ad6ad95622164686bc2cbfc9802'/>
<id>urn:sha1:7d10001e20e46ad6ad95622164686bc2cbfc9802</id>
<content type='text'>
Add a PTP clock driver called ptp_vmw, for guests running on VMware ESXi
hypervisor. The driver attaches to a VMware virtual device called
"precision clock" that provides a mechanism for querying host system time.
Similar to existing virtual PTP clock drivers (e.g. ptp_kvm), ptp_vmw
utilizes the kernel's PTP hardware clock API to implement a clock device
that can be used as a reference in Chrony for synchronizing guest time with
host.

The driver is only applicable to x86 guests running in VMware virtual
machines with precision clock virtual device present. It uses a VMware
specific hypercall mechanism to read time from the device.

Reviewed-by: Thomas Hellstrom &lt;thellstrom@vmware.com&gt;
Signed-off-by: Vivek Thampi &lt;vithampi@vmware.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>ptp: Add a ptp clock driver for IDT 82P33 SMU.</title>
<updated>2020-02-24T21:08:46Z</updated>
<author>
<name>Min Li</name>
<email>min.li.xe@renesas.com</email>
</author>
<published>2020-02-21T20:03:51Z</published>
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<id>urn:sha1:57a10d8c1123068e3cb06434fbc9634f945d3062</id>
<content type='text'>
The IDT 82P33 Synchronization Management Unit (SMU) family provides
tools to manage timing references, clock sources and
timing paths for IEEE 1588 / Precision Time Protocol (PTP) and
Synchronous Ethernet (SyncE) based clocks. The device supports up
to three independent timing paths that control: PTP clock synthesis;
SyncE clock generation; and general purpose frequency translation.
The device supports physical layer timing with Digital PLLs (DPLLs)
and it supports packet based timing with Digitally Controlled
Oscillators (DCOs). This patch adds support for ptp clock based on
the device.

Changes since v1:
 - As suggested by Richard Cochran:
   1. Replace _mask_bit_count with the existing hweight8
   2. Prefix all functions with idt82p33
   3. Fix white space issues in Kconfig and Makefile
   4. Remove forward declaration
   5. Use adjfine instead of adjfreq for better resolution

 - As suggested by David Miller:
   1. Replace CHAN_INIT macro with a static function
      idt82p33_channel_init
   2. Employ reverse christmas tree ordering for local
      variables
   3. Fix indentation problem by appropriate number of
      TAB then SPACE character

Signed-off-by: Min Li &lt;min.li.xe@renesas.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>ptp: ixp46x: move adjacent to ethernet driver</title>
<updated>2020-01-12T20:59:52Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2020-01-12T12:04:44Z</published>
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<id>urn:sha1:2785543fbf0498eb749adee3d129ba8ac139c729</id>
<content type='text'>
The ixp46x ptp driver has a somewhat unusual setup, where the ptp
driver and the ethernet driver are in different directories but
access the same registers that are defined a platform specific
header file.

Moving everything into drivers/net/ makes it look more like most
other ptp drivers and allows compile-testing this driver on
other targets.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ptp: Add a driver for InES time stamping IP core.</title>
<updated>2019-12-26T03:51:34Z</updated>
<author>
<name>Richard Cochran</name>
<email>richardcochran@gmail.com</email>
</author>
<published>2019-12-26T02:16:20Z</published>
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<id>urn:sha1:bad1eaa6ac312ffd7aa46dd5a4d9843b824aa023</id>
<content type='text'>
The InES at the ZHAW offers a PTP time stamping IP core.  The FPGA
logic recognizes and time stamps PTP frames on the MII bus.  This
patch adds a driver for the core along with a device tree binding to
allow hooking the driver to MII buses.

Signed-off-by: Richard Cochran &lt;richardcochran@gmail.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>ptp: clockmatrix: add I2C dependency</title>
<updated>2019-12-13T23:42:09Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2019-12-10T19:56:34Z</published>
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<id>urn:sha1:03b06e3f83523ded51aa822f58c083fbde08feb5</id>
<content type='text'>
Without I2C, we get a link failure:

drivers/ptp/ptp_clockmatrix.o: In function `idtcm_xfer.isra.3':
ptp_clockmatrix.c:(.text+0xcc): undefined reference to `i2c_transfer'
drivers/ptp/ptp_clockmatrix.o: In function `idtcm_driver_init':
ptp_clockmatrix.c:(.init.text+0x14): undefined reference to `i2c_register_driver'
drivers/ptp/ptp_clockmatrix.o: In function `idtcm_driver_exit':
ptp_clockmatrix.c:(.exit.text+0x10): undefined reference to `i2c_del_driver'

Fixes: 3a6ba7dc7799 ("ptp: Add a ptp clock driver for IDT ClockMatrix.")
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Reviewed-by: Vincent Cheng &lt;vincent.cheng.xh@renesas.com&gt;
Signed-off-by: Jakub Kicinski &lt;jakub.kicinski@netronome.com&gt;
</content>
</entry>
<entry>
<title>ptp: ptp_clockmatrix: Fix build error</title>
<updated>2019-11-12T20:12:39Z</updated>
<author>
<name>YueHaibing</name>
<email>yuehaibing@huawei.com</email>
</author>
<published>2019-11-12T14:35:14Z</published>
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<id>urn:sha1:1e86606ba05d5e6269dabb209f5406745cb5b141</id>
<content type='text'>
When do randbuilding, we got this warning:

WARNING: unmet direct dependencies detected for PTP_1588_CLOCK
  Depends on [n]: NET [=y] &amp;&amp; POSIX_TIMERS [=n]
  Selected by [y]:
  - PTP_1588_CLOCK_IDTCM [=y]

Make PTP_1588_CLOCK_IDTCM depends on PTP_1588_CLOCK to fix this.

Fixes: 3a6ba7dc7799 ("ptp: Add a ptp clock driver for IDT ClockMatrix.")
Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Reviewed-by: Vincent Cheng  &lt;vincent.cheng.xh@renesas.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>ptp: Add a ptp clock driver for IDT ClockMatrix.</title>
<updated>2019-11-04T01:35:40Z</updated>
<author>
<name>Vincent Cheng</name>
<email>vincent.cheng.xh@renesas.com</email>
</author>
<published>2019-11-01T03:20:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3a6ba7dc7799355557938fbdc15a558236011429'/>
<id>urn:sha1:3a6ba7dc7799355557938fbdc15a558236011429</id>
<content type='text'>
The IDT ClockMatrix (TM) family includes integrated devices that provide
eight PLL channels.  Each PLL channel can be independently configured as a
frequency synthesizer, jitter attenuator, digitally controlled
oscillator (DCO), or a digital phase lock loop (DPLL).  Typically
these devices are used as timing references and clock sources for PTP
applications.  This patch adds support for the device.

Co-developed-by: Richard Cochran &lt;richardcochran@gmail.com&gt;
Signed-off-by: Richard Cochran &lt;richardcochran@gmail.com&gt;
Signed-off-by: Vincent Cheng &lt;vincent.cheng.xh@renesas.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>ptp: fix typo of "mechanism" in Kconfig help text</title>
<updated>2019-10-07T18:55:46Z</updated>
<author>
<name>Antonio Borneo</name>
<email>antonio.borneo@st.com</email>
</author>
<published>2019-10-07T15:43:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=503c9addef613c872679e24fc8a78f3febeb5a08'/>
<id>urn:sha1:503c9addef613c872679e24fc8a78f3febeb5a08</id>
<content type='text'>
Fix typo s/mechansim/mechanism/

Signed-off-by: Antonio Borneo &lt;antonio.borneo@st.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>ptp: add QorIQ PTP support for DPAA2</title>
<updated>2019-06-15T20:43:06Z</updated>
<author>
<name>Yangbo Lu</name>
<email>yangbo.lu@nxp.com</email>
</author>
<published>2019-06-14T10:40:50Z</published>
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<id>urn:sha1:8099d7ca6e7b76282fef7565877f5c8f02f8ef4f</id>
<content type='text'>
This patch is to add QorIQ PTP support for DPAA2.
Although dpaa2-ptp.c driver is a fsl_mc_driver which
is using MC APIs for register accessing, it's same
IP block with eTSEC/DPAA/ENETC 1588 timer. We will
convert to reuse ptp_qoriq driver by using register
ioremap and dropping related MC APIs.
Also allow to compile ptp_qoriq with COMPILE_TEST.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@nxp.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>treewide: Add SPDX license identifier - Makefile/Kconfig</title>
<updated>2019-05-21T08:50:46Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-19T12:07:45Z</published>
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<id>urn:sha1:ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1</id>
<content type='text'>
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
</feed>
