<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/soundwire/intel.h, branch update-toolchain</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/soundwire/intel.h?h=update-toolchain</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/soundwire/intel.h?h=update-toolchain'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2024-06-03T12:11:11Z</updated>
<entry>
<title>soundwire: intel_ace2.x: add AC timing extensions for PantherLake</title>
<updated>2024-06-03T12:11:11Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2024-06-03T07:02:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9b5fd115e7d5a98b82054cff5c96f6768ee06845'/>
<id>urn:sha1:9b5fd115e7d5a98b82054cff5c96f6768ee06845</id>
<content type='text'>
The ACE3 IP used in PantherLake exposes new bitfields in the ACTMCTL
register to better control clocks/delays. These bitfields were
reserved/zero in the ACE2.x IP, to simplify the integration the new
bifields are added unconditionally. The behavior will only be impacted
when the firmware exposes DSD properties to set non-zero values.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Péter Ujfalusi &lt;peter.ujfalusi@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20240603070240.5165-1-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>soundwire: intel_ace2.x: add support for DOAISE property</title>
<updated>2024-05-04T12:56:50Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2024-04-29T00:43:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a0df7e04eab07cb2c08517209f792a8070504f0d'/>
<id>urn:sha1:a0df7e04eab07cb2c08517209f792a8070504f0d</id>
<content type='text'>
Extend previous patches with the DOAISE field and property.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20240429004321.2399754-5-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>soundwire: intel_ace2.x: add support for DODSE property</title>
<updated>2024-05-04T12:56:50Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2024-04-29T00:43:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=75933ba58dd49ded547ad0d00c74c0cb862530f9'/>
<id>urn:sha1:75933ba58dd49ded547ad0d00c74c0cb862530f9</id>
<content type='text'>
Extend previous patches with the DODSE field and property.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20240429004321.2399754-4-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>soundwire: intel_ace2x: use DOAIS and DODS settings from firmware</title>
<updated>2024-05-04T12:56:50Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2024-04-29T00:43:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3b0b441a297e7fe11baab51439a81cd6a336ed64'/>
<id>urn:sha1:3b0b441a297e7fe11baab51439a81cd6a336ed64</id>
<content type='text'>
Starting with LNL, the recommendation is to use settings read from DSD
properties instead of hard-coding the values.

The DOAIS and DODS values are completely-specific to Intel and are
stored in a vendor-specific property structure.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20240429004321.2399754-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>soundwire: intel_ace2x: add debugfs support</title>
<updated>2023-05-27T10:36:45Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2023-05-15T07:10:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=312316d5a16c46ae0630dda574b243dba06195c6'/>
<id>urn:sha1:312316d5a16c46ae0630dda574b243dba06195c6</id>
<content type='text'>
Add access to registers in SHIM and SHIM_VS (vendor-specific) areas.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Rander Wang &lt;rander.wang@intel.com&gt;
Reviewed-by: Péter Ujfalusi &lt;peter.ujfalusi@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20230515071042.2038-11-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC/soundwire: intel: pass hdac_bus pointer for link management</title>
<updated>2023-05-27T10:36:45Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2023-05-15T07:10:22Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=881cf1e9df731e6dc238ca83067c17c782e2a059'/>
<id>urn:sha1:881cf1e9df731e6dc238ca83067c17c782e2a059</id>
<content type='text'>
The hdac_bus pointer is used to access the extended link information
and handle power management. Pass it from the SOF driver down to the
auxiliary devices.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Rander Wang &lt;rander.wang@intel.com&gt;
Reviewed-by: Péter Ujfalusi &lt;peter.ujfalusi@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Acked-by: Mark Brown &lt;broonie@kernel.org&gt;
Link: https://lore.kernel.org/r/20230515071042.2038-7-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>soundwire: intel/cadence: set ip_offset at run-time</title>
<updated>2023-05-27T10:36:45Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2023-05-15T07:10:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e40e0e11fe64a0ac93fb11c3c448b844516bc6ee'/>
<id>urn:sha1:e40e0e11fe64a0ac93fb11c3c448b844516bc6ee</id>
<content type='text'>
Select relevant ip-offset depending on hardware version. This offset
is used to access MCP_ or IP_MCP_ registers with a fixed offset.

For existing platforms, the offset is exactly zero. Starting with
LunarLake, the offset is 0x4000.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Rander Wang &lt;rander.wang@intel.com&gt;
Reviewed-by: Péter Ujfalusi &lt;peter.ujfalusi@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20230515071042.2038-6-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>soundwire/ASOC: Intel: update offsets for LunarLake</title>
<updated>2023-05-27T10:36:45Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2023-05-15T07:10:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=6ab915b9c355caa1f80e9e383892052523f49d1f'/>
<id>urn:sha1:6ab915b9c355caa1f80e9e383892052523f49d1f</id>
<content type='text'>
The previous settings are not applicable, use a flag to determine what
the register layout is.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Rander Wang &lt;rander.wang@intel.com&gt;
Reviewed-by: Péter Ujfalusi &lt;peter.ujfalusi@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Acked-by: Mark Brown &lt;broonie@kernel.org&gt;
Link: https://lore.kernel.org/r/20230515071042.2038-5-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>soundwire: intel: move bank switch routine to common intel_bus_common.c</title>
<updated>2023-03-15T13:54:02Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2023-03-14T01:54:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=fb43d62ee772fac7173bfbed3ca1bccdc508f10a'/>
<id>urn:sha1:fb43d62ee772fac7173bfbed3ca1bccdc508f10a</id>
<content type='text'>
No functionality change, just moving the routines to a common file so
that they can be used for new hardware.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Rander Wang &lt;rander.wang@intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20230314015410.487311-11-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>soundwire: intel: add abstraction for cmdsync check</title>
<updated>2023-03-15T13:54:02Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2023-03-14T01:54:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1e76de2e5dfeff17f13afe8146449fec3f5b69f7'/>
<id>urn:sha1:1e76de2e5dfeff17f13afe8146449fec3f5b69f7</id>
<content type='text'>
If we add one more callback, we can have common bank switch sequences
between old and new hardware: the only difference is where the CMDSYNC
register is located.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Rander Wang &lt;rander.wang@intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20230314015410.487311-10-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
</feed>
