<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/ufs/host, branch jd/bump-compilers</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/ufs/host?h=jd%2Fbump-compilers</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/ufs/host?h=jd%2Fbump-compilers'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2024-08-29T01:29:20Z</updated>
<entry>
<title>scsi: ufs: ufs-mediatek: Add UFSHCD_QUIRK_BROKEN_LSDBS_CAP</title>
<updated>2024-08-29T01:29:20Z</updated>
<author>
<name>Mary Guillemard</name>
<email>mary@mary.zone</email>
</author>
<published>2024-08-18T22:24:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0f9592ae26ffe044cfb2b2d071ccf4427be57ed4'/>
<id>urn:sha1:0f9592ae26ffe044cfb2b2d071ccf4427be57ed4</id>
<content type='text'>
MT8183 implements the UFSHCI 2.1 spec but reports a bogus value of 1 in
the reserved part for the Legacy Single Doorbell Support (LSDBS)
capability.

Set UFSHCD_QUIRK_BROKEN_LSDBS_CAP when MCQ support is explicitly
disabled, allowing the device to be properly registered.

Signed-off-by: Mary Guillemard &lt;mary@mary.zone&gt;
Link: https://lore.kernel.org/r/20240818222442.44990-3-mary@mary.zone
Reviewed-by: Peter Wang &lt;peter.wang@mediatek.com&gt;
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: qcom: Add UFSHCD_QUIRK_BROKEN_LSDBS_CAP for SM8550 SoC</title>
<updated>2024-08-17T01:09:17Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2024-08-16T06:25:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ea593e028a9cc523557b4084a61d87ae69e2f270'/>
<id>urn:sha1:ea593e028a9cc523557b4084a61d87ae69e2f270</id>
<content type='text'>
SM8550 SoC has the UFSHCI 4.0 compliant UFS controller and only supports
legacy single doorbell mode without MCQ. But due to a hardware bug, it
reports 1 in the 'Legacy Queue &amp; Single Doorbell Support (LSDBS)' field of
the Controller Capabilities register. This field is supposed to read as 0
if legacy single doorbell mode is supported and 1 otherwise.

Starting with commit 0c60eb0cc320 ("scsi: ufs: core: Check LSDBS cap when
!mcq"), ufshcd driver is now relying on the LSDBS field to decide when to
use the legacy doorbell mode if MCQ is not supported. And this ends up
breaking UFS on SM8550:

ufshcd-qcom 1d84000.ufs: ufshcd_init: failed to initialize (legacy doorbell mode not supported)
ufshcd-qcom 1d84000.ufs: error -EINVAL: Initialization failed with error -22

So use the UFSHCD_QUIRK_BROKEN_LSDBS_CAP quirk for SM8550 SoC so that the
ufshcd driver could use legacy doorbell mode correctly.

Fixes: 0c60eb0cc320 ("scsi: ufs: core: Check LSDBS cap when !mcq")
Tested-by: Amit Pundir &lt;amit.pundir@linaro.org&gt;
Reviewed-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Link: https://lore.kernel.org/r/20240816-ufs-bug-fix-v3-2-e6fe0e18e2a3@linaro.org
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: exynos: Don't resume FMP when crypto support is disabled</title>
<updated>2024-07-23T00:52:15Z</updated>
<author>
<name>Eric Biggers</name>
<email>ebiggers@google.com</email>
</author>
<published>2024-07-21T18:38:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=47398f49dab8326bb652fa2d7a51ae5ec78775b5'/>
<id>urn:sha1:47398f49dab8326bb652fa2d7a51ae5ec78775b5</id>
<content type='text'>
If exynos_ufs_fmp_init() did not enable FMP support, then
exynos_ufs_fmp_resume() should not execute the FMP-related SMC calls.

Fixes: c96499fcb403 ("scsi: ufs: exynos: Add support for Flash Memory Protector (FMP)")
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240721183840.209284-1-ebiggers@kernel.org
Reviewed-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "Basic inline encryption support for ufs-exynos"</title>
<updated>2024-07-11T02:33:34Z</updated>
<author>
<name>Martin K. Petersen</name>
<email>martin.petersen@oracle.com</email>
</author>
<published>2024-07-11T02:33:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=af8e69efd78561496cdd736bb1b4f7edd89b2f6b'/>
<id>urn:sha1:af8e69efd78561496cdd736bb1b4f7edd89b2f6b</id>
<content type='text'>
Eric Biggers &lt;ebiggers@kernel.org&gt; says:

Add support for Flash Memory Protector (FMP), which is the inline
encryption hardware on Exynos and Exynos-based SoCs.

Specifically, add support for the "traditional FMP mode" that works on
many Exynos-based SoCs including gs101.  This is the mode that uses
"software keys" and is compatible with the upstream kernel's existing
inline encryption framework in the block and filesystem layers.  I
plan to add support for the wrapped key support on gs101 at a later
time.

Tested on gs101 (specifically Pixel 6) by running the 'encrypt' group
of xfstests on a filesystem mounted with the 'inlinecrypt' mount
option.

This patchset applies to v6.10-rc6, and it has no prerequisites that
aren't already upstream.

Link: https://lore.kernel.org/r/20240708235330.103590-1-ebiggers@kernel.org
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: exynos: Add support for Flash Memory Protector (FMP)</title>
<updated>2024-07-11T02:32:30Z</updated>
<author>
<name>Eric Biggers</name>
<email>ebiggers@google.com</email>
</author>
<published>2024-07-08T23:53:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c96499fcb403b18b0ae0bf2e19a39f24e62dd3ac'/>
<id>urn:sha1:c96499fcb403b18b0ae0bf2e19a39f24e62dd3ac</id>
<content type='text'>
Add support for Flash Memory Protector (FMP), which is the inline
encryption hardware on Exynos and Exynos-based SoCs.

Specifically, add support for the "traditional FMP mode" that works on many
Exynos-based SoCs including gs101.  This is the mode that uses "software
keys" and is compatible with the upstream kernel's existing inline
encryption framework in the block and filesystem layers.  I plan to add
support for the wrapped key support on gs101 at a later time.

Tested on gs101 (specifically Pixel 6) by running the 'encrypt' group of
xfstests on a filesystem mounted with the 'inlinecrypt' mount option.

Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Link: https://lore.kernel.org/r/20240708235330.103590-7-ebiggers@kernel.org
Reviewed-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Tested-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Reviewed-by: Alim Akhtar &lt;alim.akhtar@samsung.com&gt;
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "UFS patches for kernel 6.11"</title>
<updated>2024-07-11T02:26:08Z</updated>
<author>
<name>Martin K. Petersen</name>
<email>martin.petersen@oracle.com</email>
</author>
<published>2024-07-11T02:26:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e30618a480cbbfc1f49ec65fea86766141b7a1df'/>
<id>urn:sha1:e30618a480cbbfc1f49ec65fea86766141b7a1df</id>
<content type='text'>
Bart Van Assche &lt;bvanassche@acm.org&gt; says:

Hi Martin,

Please consider this series of UFS driver patches for the next merge window.

Thank you,

Bart.

Link: https://lore.kernel.org/r/20240708211716.2827751-1-bvanassche@acm.org
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: core: Inline is_mcq_enabled()</title>
<updated>2024-07-11T02:19:05Z</updated>
<author>
<name>Bart Van Assche</name>
<email>bvanassche@acm.org</email>
</author>
<published>2024-07-08T21:16:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0fca3318e550d48e9a6c844763bf9eab91c30f07'/>
<id>urn:sha1:0fca3318e550d48e9a6c844763bf9eab91c30f07</id>
<content type='text'>
Improve code readability by inlining is_mcq_enabled().

Cc: Peter Wang &lt;peter.wang@mediatek.com&gt;
Cc: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Link: https://lore.kernel.org/r/20240708211716.2827751-7-bvanassche@acm.org
Reviewed-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: qcom: Enable suspending clk scaling on no request</title>
<updated>2024-07-05T02:48:33Z</updated>
<author>
<name>Ram Prakash Gupta</name>
<email>quic_rampraka@quicinc.com</email>
</author>
<published>2024-06-27T08:37:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ed7dac86f1406d73aed21d0cd1563922031a2fd8'/>
<id>urn:sha1:ed7dac86f1406d73aed21d0cd1563922031a2fd8</id>
<content type='text'>
Enable suspending clk scaling on no request for Qualcomm SoC.

Signed-off-by: Ram Prakash Gupta &lt;quic_rampraka@quicinc.com&gt;
Link: https://lore.kernel.org/r/20240627083756.25340-3-quic_rampraka@quicinc.com
Reviewed-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: ufs-pci: Add support for Intel Panther Lake</title>
<updated>2024-06-27T03:21:10Z</updated>
<author>
<name>Adrian Hunter</name>
<email>adrian.hunter@intel.com</email>
</author>
<published>2024-06-18T07:31:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=bdee2f1dcd84dcd76d9557cf55e8f3662c6506eb'/>
<id>urn:sha1:bdee2f1dcd84dcd76d9557cf55e8f3662c6506eb</id>
<content type='text'>
Add PCI ID to support Intel Panther Lake, same as MTL.

Signed-off-by: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Link: https://lore.kernel.org/r/20240618073158.38504-1-adrian.hunter@intel.com
Reviewed-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: qcom: Add missing MODULE_DESCRIPTION() macro</title>
<updated>2024-06-27T02:50:59Z</updated>
<author>
<name>Jeff Johnson</name>
<email>quic_jjohnson@quicinc.com</email>
</author>
<published>2024-06-25T16:53:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=4d66ecc6e5a5df965b43edace2d41d19ed15a2ea'/>
<id>urn:sha1:4d66ecc6e5a5df965b43edace2d41d19ed15a2ea</id>
<content type='text'>
With ARCH=arm64, make allmodconfig &amp;&amp; make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/ufs/host/ufs-qcom.o

Add the missing invocation of the MODULE_DESCRIPTION() macro.

Signed-off-by: Jeff Johnson &lt;quic_jjohnson@quicinc.com&gt;
Link: https://lore.kernel.org/r/20240625-md-drivers-ufs-host-v2-1-59a56974b05a@quicinc.com
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
</feed>
