<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/usb/dwc2/params.c, branch jd/bump-compilers</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/usb/dwc2/params.c?h=jd%2Fbump-compilers</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/usb/dwc2/params.c?h=jd%2Fbump-compilers'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2024-07-10T11:56:32Z</updated>
<entry>
<title>usb: dwc2: add support for other Lantiq SoCs</title>
<updated>2024-07-10T11:56:32Z</updated>
<author>
<name>Hauke Mehrtens</name>
<email>hauke@hauke-m.de</email>
</author>
<published>2024-07-08T22:20:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5af43708d21c30e2f418cb25d337779c56d235f6'/>
<id>urn:sha1:5af43708d21c30e2f418cb25d337779c56d235f6</id>
<content type='text'>
The size of the internal RAM of the DesignWare USB controller changed
between the different Lantiq SoCs. We have the following sizes:

Amazon + Danube: 8 KByte
Amazon SE + arx100: 2 KByte
xrx200 + xrx300: 2.5 KByte

For Danube SoC we do not provide the params and let the driver decide
to use sane defaults, for the Amazon SE and arx100 we use small fifos
and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
The auto detection of max_transfer_size and max_packet_count should
work, so remove it.

This patch is included in OpenWrt for many years.

Signed-off-by: Hauke Mehrtens &lt;hauke@hauke-m.de&gt;
Acked-by: Minas Harutyunyan &lt;hminas@synopsys.com&gt;
Link: https://lore.kernel.org/r/20240708222054.2727789-1-hauke@hauke-m.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc2: add support for Sophgo CV18XX/SG200X series SoC</title>
<updated>2024-03-27T06:57:15Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2024-03-26T02:37:29Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=63aa7ab955e7d028d3be59ebc2960e105497c70d'/>
<id>urn:sha1:63aa7ab955e7d028d3be59ebc2960e105497c70d</id>
<content type='text'>
Add params for DWC2 IP in Sophgo CV18XX/SG200X series SoC.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Acked-by: Minas Harutyunyan &lt;hminas@synopsys.com&gt;
Link: https://lore.kernel.org/r/IA1PR20MB4953EE73DD36D5FFC81D90EDBB352@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc2: Add new parameter eusb2_disc</title>
<updated>2024-03-26T09:44:53Z</updated>
<author>
<name>Minas Harutyunyan</name>
<email>Minas.Harutyunyan@synopsys.com</email>
</author>
<published>2024-03-13T09:19:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=bc5d81b8012ce51e0ed137500d92c6b146e45732'/>
<id>urn:sha1:bc5d81b8012ce51e0ed137500d92c6b146e45732</id>
<content type='text'>
Added new parameter eusb2_disc to list of core parameters which specify
whether eUSB2 PHY disconnect support flow applicable or no.
Set to false as default value and checked core version if set to true.
This parameter applicable in device mode of HSOTG and HS IOT cores
v5.00 or higher.

Added print this parameter in show parameters of debugfs.

Signed-off-by: Minas Harutyunyan &lt;Minas.Harutyunyan@synopsys.com&gt;
Link: https://lore.kernel.org/r/e77cc4312bda797d1ddaa4351d86c65a69c8b926.1708948356.git.Minas.Harutyunyan@synopsys.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc2: Disable clock gating feature on Rockchip SoCs</title>
<updated>2024-01-02T13:35:23Z</updated>
<author>
<name>William Wu</name>
<email>william.wu@rock-chips.com</email>
</author>
<published>2023-12-26T07:19:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ca2dc35e555e7043de585f4e46123d8fbd2b5a21'/>
<id>urn:sha1:ca2dc35e555e7043de585f4e46123d8fbd2b5a21</id>
<content type='text'>
The DWC2 IP on the Rockchip SoCs doesn't support clock gating.
When a clock gating is enabled, system hangs.

Signed-off-by: William Wu &lt;william.wu@rock-chips.com&gt;
Acked-by: Minas Harutyunyan &lt;hminas@synopsys.com&gt;
Link: https://lore.kernel.org/r/1703575199-23638-1-git-send-email-william.wu@rock-chips.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: Use device_get_match_data()</title>
<updated>2023-10-10T06:55:23Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2023-10-09T21:13:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=14485de431b0a860d3a117fe518ce9ede8c76732'/>
<id>urn:sha1:14485de431b0a860d3a117fe518ce9ede8c76732</id>
<content type='text'>
Use preferred device_get_match_data() instead of of_match_device() to
get the driver match data. With this, adjust the includes to explicitly
include the correct headers.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20231009211356.3242037-16-robh@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc2: add pci_device_id driver_data parse support</title>
<updated>2023-08-22T12:49:12Z</updated>
<author>
<name>Yinbo Zhu</name>
<email>zhuyinbo@loongson.cn</email>
</author>
<published>2023-08-15T06:58:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e16d5f1447e0fae6cbcd1d430b20f87b65f25307'/>
<id>urn:sha1:e16d5f1447e0fae6cbcd1d430b20f87b65f25307</id>
<content type='text'>
The dwc2 driver has everything we need to run in PCI mode except
for pci_device_id driver_data parse.  With that to set Loongson
dwc2 element and added identified as PCI_VENDOR_ID_LOONGSON
and PCI_DEVICE_ID_LOONGSON_DWC2 in dwc2_pci_ids, the Loongson
dwc2 controller will work.

Signed-off-by: Yinbo Zhu &lt;zhuyinbo@loongson.cn&gt;
Link: https://lore.kernel.org/r/20230815065833.3375-1-zhuyinbo@loongson.cn
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc2: support dwc2 IP for Amlogic A1 SoC family</title>
<updated>2023-05-13T10:03:24Z</updated>
<author>
<name>Dmitry Rokosov</name>
<email>ddrokosov@sberdevices.ru</email>
</author>
<published>2023-05-11T21:04:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=be877fbf8968f870279c8384b41c6bd6c3863068'/>
<id>urn:sha1:be877fbf8968f870279c8384b41c6bd6c3863068</id>
<content type='text'>
The Amlogic A1 uses dwc2 Synopsys IP as its USB peripheral (gadget)
endpoint, with different DWC2 parameters when compared to previous
Amlogic SoCs.

Signed-off-by: Dmitry Rokosov &lt;ddrokosov@sberdevices.ru&gt;
Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Acked-by: Minas Harutyunyan &lt;Minas.Harutyunyan@synopsys.com&gt;
Link: https://lore.kernel.org/r/20230511210455.6634-2-ddrokosov@sberdevices.ru
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: Use of_property_read_bool() for boolean properties</title>
<updated>2023-03-16T11:14:56Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2023-03-10T14:47:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f977caea50381e9ca38319037a2b23fe3209d647'/>
<id>urn:sha1:f977caea50381e9ca38319037a2b23fe3209d647</id>
<content type='text'>
It is preferred to use typed property access functions (i.e.
of_property_read_&lt;type&gt; functions) rather than low-level
of_get_property/of_find_property functions for reading properties.
Convert reading boolean properties to to of_property_read_bool().

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Richard Leitner &lt;richard.leitner@skidata.com&gt;
Link: https://lore.kernel.org/r/20230310144729.1545857-1-robh@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc2: disable lpm feature on Rockchip SoCs</title>
<updated>2022-12-08T15:50:56Z</updated>
<author>
<name>Quentin Schulz</name>
<email>quentin.schulz@theobroma-systems.com</email>
</author>
<published>2022-12-07T13:19:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=42a317d076b58f08413219b1679d211783c2e5f3'/>
<id>urn:sha1:42a317d076b58f08413219b1679d211783c2e5f3</id>
<content type='text'>
LPM feature of DWC2 module integrated in Rockchip SoCs doesn't work
properly or needs some additional handling, so disable it for now.
Without disabling LPM feature, the USB ADB communication fail with
the following error log:

dwc2 ff580000.usb: new address 27
dwc2 ff580000.usb: Failed to exit L1 sleep state in 200us.
dwc2 ff580000.usb: dwc2_hsotg_send_reply: cannot queue req
dwc2 ff580000.usb: dwc2_hsotg_process_req_status: failed to send reply
dwc2 ff580000.usb: dwc2_hsotg_enqueue_setup: failed queue (-11)
dwc2 ff580000.usb: Failed to exit L1 sleep state in 200us.

[diff vs vendor kernel: added lpm_clock_gating, besl and
 hird_threshold_en settings as seen in  commit 53febc956900 ("usb: dwc2:
 disable Link Power Management on STM32MP15 HS OTG")]

Signed-off-by: William Wu &lt;william.wu@rock-chips.com&gt;
Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Signed-off-by: Quentin Schulz &lt;quentin.schulz@theobroma-systems.com&gt;
Link: https://lore.kernel.org/r/20221206-dwc2-gadget-dual-role-v1-1-36515e1092cd@theobroma-systems.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>usb: dwc2: Remove redundant license text</title>
<updated>2022-09-22T13:52:29Z</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2022-09-10T05:46:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b4e05668348edea7f39bf4dc80be0c0c4ca9ed4b'/>
<id>urn:sha1:b4e05668348edea7f39bf4dc80be0c0c4ca9ed4b</id>
<content type='text'>
SPDX-License-Identifier have been added in commit 5fd54ace4721 ("USB: add
SPDX identifiers to all remaining files in drivers/usb/")

There is no point in keeping the now redundant license text.

Remove it.

Acked-by: Minas Harutyunyan &lt;hminas@synopsys.com&gt;
Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Link: https://lore.kernel.org/r/030a7e187d707f8734a492cda7a6b54d459c4bb3.1662788747.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
</feed>
