<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers, branch devel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers?h=devel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers?h=devel'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2026-05-05T12:40:39Z</updated>
<entry>
<title>net: eth: fbnic: Add pma read and write access</title>
<updated>2026-05-05T12:40:39Z</updated>
<author>
<name>Mike Marciniszyn (Meta)</name>
<email>mike.marciniszyn@gmail.com</email>
</author>
<published>2026-04-30T15:08:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3877097c3c9e0356ad5ed8411f417a100090be9c'/>
<id>urn:sha1:3877097c3c9e0356ad5ed8411f417a100090be9c</id>
<content type='text'>
Document the MDIO interface topology with an ASCII diagram
showing the MAC, PCS (MMD 3), FEC, Separated PMA (MMD 8), and PMD
(MMD 1) blocks and their interconnects. The diagram illustrates how
4 lanes connect the MAC through PCS, FEC, and PMA, then narrow to
2 lanes at the PMD.

The c45 read and write routines are enhanced to support
read and write of the separated PMA for the fbnic.

Co-developed-by: Alexander Duyck &lt;alexanderduyck@fb.com&gt;
Signed-off-by: Alexander Duyck &lt;alexanderduyck@fb.com&gt;
Signed-off-by: Mike Marciniszyn (Meta) &lt;mike.marciniszyn@gmail.com&gt;
Link: https://patch.msgid.link/20260430150802.3521-4-mike.marciniszyn@gmail.com
Signed-off-by: Paolo Abeni &lt;pabeni@redhat.com&gt;
</content>
</entry>
<entry>
<title>net: eth: fbnic: Consolidate register reads for ids and devs</title>
<updated>2026-05-05T12:40:39Z</updated>
<author>
<name>Mike Marciniszyn (Meta)</name>
<email>mike.marciniszyn@gmail.com</email>
</author>
<published>2026-04-30T15:08:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d7dbf00b4a5503def75487ed803698042ba1965d'/>
<id>urn:sha1:d7dbf00b4a5503def75487ed803698042ba1965d</id>
<content type='text'>
Consolidate the register reads for boiler plate registers
to reduce LOC and cleanup pcs reads for DEVS1 to
fetch overrides for reserved bits that the hardware does not
return.

Signed-off-by: Mike Marciniszyn (Meta) &lt;mike.marciniszyn@gmail.com&gt;
Link: https://patch.msgid.link/20260430150802.3521-3-mike.marciniszyn@gmail.com
Signed-off-by: Paolo Abeni &lt;pabeni@redhat.com&gt;
</content>
</entry>
<entry>
<title>net: airoha: Introduce airoha_fe_get()/airoha_qdma_get() register read helpers</title>
<updated>2026-05-05T02:31:02Z</updated>
<author>
<name>Lorenzo Bianconi</name>
<email>lorenzo@kernel.org</email>
</author>
<published>2026-05-01T07:49:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=98e490930de3af9afa0bbb2d1d79d6d5b5513012'/>
<id>urn:sha1:98e490930de3af9afa0bbb2d1d79d6d5b5513012</id>
<content type='text'>
Add airoha_fe_get() and airoha_qdma_get() as utility routines for reading
a masked field from a specified register.
This is a non-functional refactor, no logical changes are introduced to
the existing codebase.

Signed-off-by: Lorenzo Bianconi &lt;lorenzo@kernel.org&gt;
Link: https://patch.msgid.link/20260501-airoha_fe_get-airoha_qdma_get-v3-1-126c6f647ccb@kernel.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: replace magic number with register bit macros</title>
<updated>2026-05-05T02:22:21Z</updated>
<author>
<name>Aleksander Jan Bajkowski</name>
<email>olek2@wp.pl</email>
</author>
<published>2026-05-02T09:28:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=052065add1b5acaba235e7ca7f0354edac3116c6'/>
<id>urn:sha1:052065add1b5acaba235e7ca7f0354edac3116c6</id>
<content type='text'>
Replace magic number with register bit macros. The description of
the RTL8211B interrupt register is obtained from publicly available
datasheet (RTL8211B(L) Rev. 1.5 Datasheet)

Signed-off-by: Aleksander Jan Bajkowski &lt;olek2@wp.pl&gt;
Reviewed-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Link: https://patch.msgid.link/20260502092857.156831-1-olek2@wp.pl
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: mana: hardening: Reject zero max_num_queues from GDMA_QUERY_MAX_RESOURCES</title>
<updated>2026-05-05T02:13:36Z</updated>
<author>
<name>Erni Sri Satya Vennela</name>
<email>ernis@linux.microsoft.com</email>
</author>
<published>2026-04-30T08:36:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f7622e58e8022190774cbbb7724d16f286aeb215'/>
<id>urn:sha1:f7622e58e8022190774cbbb7724d16f286aeb215</id>
<content type='text'>
In a CVM environment, hardware responses cannot be trusted. The
GDMA_QUERY_MAX_RESOURCES command returns resource limits used to
determine the maximum number of queues.

In mana_gd_query_max_resources(), gc-&gt;max_num_queues is initialized
from num_online_cpus() and successively clamped by the hardware-reported
max_eq, max_cq, max_sq, max_rq, and num_msix_usable values. If any of
these hardware values is zero, gc-&gt;max_num_queues becomes zero and the
function returns success. This leads to a confusing failure later when
alloc_etherdev_mq() is called with zero queues, returning NULL and
producing a misleading -ENOMEM error.

Add an explicit zero check for gc-&gt;max_num_queues after all clamping
steps and return -ENOSPC for a clear early failure, consistent with the
existing gc-&gt;num_msix_usable &lt;= 1 guard.

Signed-off-by: Erni Sri Satya Vennela &lt;ernis@linux.microsoft.com&gt;
Reviewed-by: Shradha Gupta &lt;shradhagupta@linux.microsoft.com&gt;
Link: https://patch.msgid.link/20260430083627.1873757-1-ernis@linux.microsoft.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: mana: hardening: Reject zero max_num_queues from MANA_QUERY_VPORT_CONFIG</title>
<updated>2026-05-05T02:13:31Z</updated>
<author>
<name>Erni Sri Satya Vennela</name>
<email>ernis@linux.microsoft.com</email>
</author>
<published>2026-04-30T08:56:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=93ca1575dd1f43e24ad85663305e13114f9acdf1'/>
<id>urn:sha1:93ca1575dd1f43e24ad85663305e13114f9acdf1</id>
<content type='text'>
As a part of MANA hardening for CVM, validate that max_num_sq and
max_num_rq returned by MANA_QUERY_VPORT_CONFIG are not zero. These
values flow into apc-&gt;num_queues, which is used as an allocation count
and loop bound. A zero value would result in zero-size allocations and
incorrect driver behavior.

Return -EPROTO if either value is zero.

Signed-off-by: Erni Sri Satya Vennela &lt;ernis@linux.microsoft.com&gt;
Link: https://patch.msgid.link/20260430085638.1875400-1-ernis@linux.microsoft.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: Add support for PHY LEDs on RTL8221B</title>
<updated>2026-05-05T01:38:36Z</updated>
<author>
<name>Chukun Pan</name>
<email>amadeus@jmu.edu.cn</email>
</author>
<published>2026-05-01T10:00:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d3aae4d954f92a273388439ab015763e0cdea1e0'/>
<id>urn:sha1:d3aae4d954f92a273388439ab015763e0cdea1e0</id>
<content type='text'>
Realtek RTL8221B Ethernet PHY supports three LED pins which are used to
indicate link status and activity. Add netdev trigger support for them.

Signed-off-by: Chukun Pan &lt;amadeus@jmu.edu.cn&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Link: https://patch.msgid.link/20260501100002.755672-1-amadeus@jmu.edu.cn
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ice: dpll: Fix compilation warning</title>
<updated>2026-05-03T02:12:47Z</updated>
<author>
<name>Przemyslaw Korba</name>
<email>przemyslaw.korba@intel.com</email>
</author>
<published>2026-05-01T06:37:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=586483cb41f40eab03ca65ceedeae623b379783a'/>
<id>urn:sha1:586483cb41f40eab03ca65ceedeae623b379783a</id>
<content type='text'>
Introduced by commit ad1df4f2d591 ("ice: dpll: Support E825-C SyncE and
dynamic pin discovery"):

ice_dpll.c: In function ‘ice_dpll_init’:
ice_dpll.c:3588:59: error: ‘%u’ directive output may be truncated
writing between 1 and 10 bytes into a region of size 4
[-Werror=format-truncation=] snprintf(pin_name, sizeof(pin_name),
"rclk%u", i);

Reviewed-by: Przemek Kitszel &lt;przemyslaw.kitszel@intel.com&gt;
Signed-off-by: Przemyslaw Korba &lt;przemyslaw.korba@intel.com&gt;
Reviewed-by: Aleksandr Loktionov &lt;aleksandr.loktionov@intel.com&gt;
Signed-off-by: Jacob Keller &lt;jacob.e.keller@intel.com&gt;
Link: https://patch.msgid.link/20260430-jk-iwl-net-next-2026-04-30-v1-13-6f27ae1cd073@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ice: access @pp through netmem_desc instead of page</title>
<updated>2026-05-03T02:12:46Z</updated>
<author>
<name>Byungchul Park</name>
<email>byungchul@sk.com</email>
</author>
<published>2026-05-01T06:37:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b9fa4b9e051bd888907b0366bbd3d88dd9281372'/>
<id>urn:sha1:b9fa4b9e051bd888907b0366bbd3d88dd9281372</id>
<content type='text'>
To eliminate the use of struct page in page pool, the page pool users
should use netmem descriptor and APIs instead.

Make ice driver access @pp through netmem_desc instead of page.

Signed-off-by: Byungchul Park &lt;byungchul@sk.com&gt;
Tested-by: Alexander Nowlin &lt;alexander.nowlin@intel.com&gt;
Tested-by: Rinitha S &lt;sx.rinitha@intel.com&gt;
Reviewed-by: David Hildenbrand (Arm) &lt;david@kernel.org&gt;
Signed-off-by: Jacob Keller &lt;jacob.e.keller@intel.com&gt;
Link: https://patch.msgid.link/20260430-jk-iwl-net-next-2026-04-30-v1-12-6f27ae1cd073@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ice: mention fw_activate action along with devlink reload</title>
<updated>2026-05-03T02:12:46Z</updated>
<author>
<name>Jacob Keller</name>
<email>jacob.e.keller@intel.com</email>
</author>
<published>2026-05-01T06:37:22Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3f923a48dac0584270c32296d49e0c70b067e4f3'/>
<id>urn:sha1:3f923a48dac0584270c32296d49e0c70b067e4f3</id>
<content type='text'>
The ice driver reports a helpful status message when updating firmware
indicating what action is necessary to enable the new firmware. This is
done because some updates require power cycling or rebooting the machine
but some can be activated via devlink.

The ice driver only supports activating firmware with the specific action
of "fw_activate" a bare "devlink dev reload" will *not* update the
firmware, and will only perform driver reinitialization.

Update the status message to explicitly reflect that the reload must use
the fw_activate action.

I considered modifying the text to spell out the full command, but felt
that was both overkill and something that would belong better as part of
the user space program and not hard coded into the kernel driver output.

Reviewed-by: Aleksandr Loktionov &lt;aleksandr.loktionov@intel.com&gt;
Reviewed-by: Przemek Kitszel &lt;przemyslaw.kitszel@intel.com&gt;
Reviewed-by: Simon Horman &lt;horms@kernel.org&gt;
Signed-off-by: Jacob Keller &lt;jacob.e.keller@intel.com&gt;
Link: https://patch.msgid.link/20260430-jk-iwl-net-next-2026-04-30-v1-11-6f27ae1cd073@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
</feed>
