<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/include/asm-arm/memory.h, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/include/asm-arm/memory.h?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/include/asm-arm/memory.h?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2008-08-02T20:32:35Z</updated>
<entry>
<title>[ARM] move include/asm-arm to arch/arm/include/asm</title>
<updated>2008-08-02T20:32:35Z</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2008-08-02T09:55:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=4baa9922430662431231ac637adedddbb0cfb2d7'/>
<id>urn:sha1:4baa9922430662431231ac637adedddbb0cfb2d7</id>
<content type='text'>
Move platform independent header files to arch/arm/include/asm, leaving
those in asm/arch* and asm/plat* alone.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>[ARM] Add initial sparsemem support</title>
<updated>2008-04-19T10:36:48Z</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2006-11-30T20:43:51Z</published>
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<id>urn:sha1:05944d74bc28fffbcce159cb915d0acff82f30a1</id>
<content type='text'>
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>[ARM] Clean up discontigmem support</title>
<updated>2006-11-30T22:52:28Z</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2006-11-30T20:39:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b7dc96d75309346c1213875be68fdbbec92da5e7'/>
<id>urn:sha1:b7dc96d75309346c1213875be68fdbbec92da5e7</id>
<content type='text'>
Most architectures have fairly simple discontiguous memory - a
simple set of successive regions each containing some memory.
These can be described simply as a log2 of their maximum size,
along with the base address of the first region and the number
of regions.

The base address is already described by PHYS_PFN_OFFSET, and
the number of regions via the MAX_NUMNODES and the number of
online nodes.

If we then supply the log2 of their maximum size, all the other
discontigmem macros can move into generic code.

There is one exception: lh7a40x seems to have a more complicated
setup; this is left alone.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>[ARM] 3705/1: add supersection support to ioremap()</title>
<updated>2006-07-01T18:58:20Z</updated>
<author>
<name>Lennert Buytenhek</name>
<email>buytenh@wantstofly.org</email>
</author>
<published>2006-07-01T18:58:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a069c896d0d6c028581089da7a9a9037a63c2803'/>
<id>urn:sha1:a069c896d0d6c028581089da7a9a9037a63c2803</id>
<content type='text'>
Patch from Lennert Buytenhek

Analogous to the previous patch that allows ioremap() to use section
mappings, this patch allows ioremap() to use supersection mappings.
Original patch by Deepak Saxena.

Signed-off-by: Lennert Buytenhek &lt;buytenh@wantstofly.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>[ARM] Add section support to ioremap</title>
<updated>2006-06-29T21:14:30Z</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2006-06-29T19:17:15Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ff0daca525dde796382b9ccd563f169df2571211'/>
<id>urn:sha1:ff0daca525dde796382b9ccd563f169df2571211</id>
<content type='text'>
Allow section mappings to be setup using ioremap() and torn down
with iounmap().  This requires additional support in the MM
context switch to ensure that mappings are properly synchronised
when mapped in.

Based an original implementation by Deepak Saxena, reworked and
ARMv6 support added by rmk.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>[ARM] nommu: adjust headers for !MMU ARM systems</title>
<updated>2006-06-28T16:59:45Z</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2006-06-20T19:46:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=002547b4f86c27bfac5bae344b723d250857be6b'/>
<id>urn:sha1:002547b4f86c27bfac5bae344b723d250857be6b</id>
<content type='text'>
Majorily based on Hyok Choi's patches, this fixes up the asm-arm
header files for mmuless systems.  Over and above Hyok's patches:

- nommu.h merged into mmu.h (it's only a structure)
- nommu_context.h is essentially the same as mmu_context.h, but
  without the MM switching code.

so there's no point having separate files.  Also, in memory.h,
there's no point #ifndef'ing PHYS_OFFSET and END_MEM - both
CONFIG_DRAM_BASE and CONFIG_DRAM_SIZE will always be set by the
configuration scripts.

Other files have minor formatting changes, but are essentially
the same.  Hyok's original patches were signed off thusly:

  Signed-off-by: Hyok S. Choi &lt;hyok.choi@samsung.com&gt;

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>Don't include linux/config.h from anywhere else in include/</title>
<updated>2006-04-26T11:56:16Z</updated>
<author>
<name>David Woodhouse</name>
<email>dwmw2@infradead.org</email>
</author>
<published>2006-04-26T11:56:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f'/>
<id>urn:sha1:62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f</id>
<content type='text'>
Signed-off-by: David Woodhouse &lt;dwmw2@infradead.org&gt;
</content>
</entry>
<entry>
<title>[ARM] Remove unnecessary extra parens in include/asm-arm/memory.h</title>
<updated>2006-04-04T15:25:47Z</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2006-04-04T15:25:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7d12963757b9170f162f317b7461353c5fb574e8'/>
<id>urn:sha1:7d12963757b9170f162f317b7461353c5fb574e8</id>
<content type='text'>
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>[ARM] arm's arch_local_page_offset() fix against 2.6.17-rc1</title>
<updated>2006-04-04T15:06:00Z</updated>
<author>
<name>KAMEZAWA Hiroyuki</name>
<email>kamezawa.hiroyu@jp.fujitsu.com</email>
</author>
<published>2006-04-04T15:06:00Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0da323505fc7dd6b01d35e6181cb3d45f992726a'/>
<id>urn:sha1:0da323505fc7dd6b01d35e6181cb3d45f992726a</id>
<content type='text'>
This patch fixes arch_local_page_offset(pfn,nid) in arm.
This new one (added by unify_pfn_to_page patches) is obviously buggy.

This macro calculate page offset in a node.

Note: about LOCAL_MAP_NR()
comment in arm's sub-archs says...

 /*
  * Given a kaddr, LOCAL_MAP_NR finds the owning node of the memory
  * and returns the index corresponding to the appropriate page in the
  * node's mem_map.
  */

but LOCAL_MAP_NR() is designed to be able to take both paddr and kaddr.
In this case, paddr is better.

Signed-off-by: KAMEZAWA Hiroyuki &lt;kamezawa.hiroyu@jp.fujitu.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
<entry>
<title>[ARM] 3439/2: xsc3: add I/O coherency support</title>
<updated>2006-04-01T23:07:39Z</updated>
<author>
<name>Lennert Buytenhek</name>
<email>buytenh@wantstofly.org</email>
</author>
<published>2006-04-01T23:07:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=23759dc6430428897a36c4d493f611eca55c9481'/>
<id>urn:sha1:23759dc6430428897a36c4d493f611eca55c9481</id>
<content type='text'>
Patch from Lennert Buytenhek

This patch adds support for the I/O coherent cache available on the
xsc3.  The approach is to provide a simple API to determine whether the
chipset supports coherency by calling arch_is_coherent() and then
setting the appropriate system memory PTE and PMD bits.  In addition,
we call this API on dma_alloc_coherent() and dma_map_single() calls.
A generic version exists that will compile out all the coherency-related
code that is not needed on the majority of ARM systems.

Note that we do not check for coherency in the dma_alloc_writecombine()
function as that still requires a special PTE setting.  We also don't
touch dma_mmap_coherent() as that is a special ARM-only API that is by
definition only used on non-coherent system.

Signed-off-by: Deepak Saxena &lt;dsaxena@plexity.net&gt;
Signed-off-by: Lennert Buytenhek &lt;buytenh@wantstofly.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
</entry>
</feed>
