wireguard-linux/include/asm-mips/cpu-features.h, branch stable

MIPS: Move headfiles to new location below arch/mips/include

2008-10-11T15:18:52Z

Signed-off-by: Ralf Baechle

[MIPS] Fix use of smp_processor_id() in preemptible code.

2007-12-01T00:39:37Z

Freeing prom memory: 956kb freed Freeing firmware memory: 978944k freed Freeing unused kernel memory: 180k freed BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1 caller is r4k_dma_cache_wback_inv+0x144/0x2a0 Call Trace: [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0 ... CONFIG_DEBUG_PREEMPT is enabled. -- Bug cause is blast_dcache_range() in preemptible code [in r4k_dma_cache_wback_inv()]. blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that uses cpu_dcache_line_size(). It uses current_cpu_data that use smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT smp_processor_id emits BUG if we are executing with preemption enabled. Cpu options of cpu0 are assumed to be the superset of all processors. Can I make the same assumptions for cache line size and fix this issue the following way: Signed-off-by: Ralf Baechle

[MIPS] Allow hardwiring of the CPU type to a single type for optimization.

2007-10-11T22:46:15Z

This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle

[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

2007-10-11T22:46:05Z

It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle

[MIPS] Enable support for the userlocal hardware register

2007-07-10T16:33:02Z

Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle

[MIPS] FPU ownership management & preemption fixes

2007-03-17T01:03:26Z

Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle

[MIPS] Use the proper technical term for naming some of the cache macros.

2006-07-13T20:26:04Z

Signed-off-by: Ralf Baechle

[MIPS] Default cpu_has_mipsmt to a runtime check

2006-07-13T20:25:58Z

Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle

[MIPS] Fix configuration of R2 CPU features and multithreading.

2006-06-29T20:10:51Z

Signed-off-by: Ralf Baechle

Don't include linux/config.h from anywhere else in include/

2006-04-26T11:56:16Z

Signed-off-by: David Woodhouse