wireguard-linux/include/asm-sh/pgtable.h, branch stable

sh: migrate to arch/sh/include/

2008-07-28T23:09:44Z

This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg Signed-off-by: Paul Mundt

sh: Stub in page_table_range_init() on nommu.

2008-01-28T04:19:00Z

Signed-off-by: Paul Mundt

sh: Clean up places that make 29-bit physical assumptions.

2008-01-28T04:18:59Z

Signed-off-by: Stuart Menefy Signed-off-by: Paul Mundt

sh: SH-5 uses a 64-bit PTE_MAGNITUDE, as X2 TLB.

2008-01-28T04:18:52Z

Signed-off-by: Paul Mundt

sh: Split out pgtable.h in to _32 and _64 variants.

2008-01-28T04:18:47Z

Signed-off-by: Paul Mundt

sh: Fix up VMALLOC_START for SH-5.

2008-01-28T04:18:44Z

Signed-off-by: Paul Mundt

sh: Split out 29-bit and 32-bit physical mode definitions.

2008-01-28T04:18:42Z

Signed-off-by: Paul Mundt

sh: Fix up PAGE_KERNEL_PCC() for nommu.

2007-11-07T02:40:24Z

PAGE_KERNEL_PCC() takes two arguments, which weren't reflected in the nommu case. Fix it up. Signed-off-by: Paul Mundt

sh: Correct pte_page() breakage.

2007-10-29T23:44:13Z

As noted by David: pte_page() is a macro defined as follows; include/asm-sh/pgtable.h #define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK) include/asm-sh/page.h #define phys_to_page(phys) (pfn_to_page(phys >> PAGE_SHIFT)) So as you can see the phys_to_page() macro doesn't wrap the 'phys' parameter in parentheses so we end up with; pte_val(x)&PTE_PHYS_MASK >> PAGE_SHIFT Which is not what we wanted as '>>' has a higher precedence than bitwise AND. I dug into the git repository and I believe this bug was added with this commit (104b8deaa5c0144cccfc7d914413ff80c7176af1); 2006-03-27 KAMEZAWA Hiroyuki [PATCH] unify pfn_to_page: sh pfn_to_page -#define phys_to_page(phys) (mem_map + (((phys)-__MEMORY_START) >> PAGE_SHIFT)) -#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + __MEMORY_START) +#define phys_to_page(phys) (pfn_to_page(phys >> PAGE_SHIFT)) +#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) Reported-by: David ADDISON Reported-by: KAMEZAWA Hiroyuki Signed-off-by: Paul Mundt

sh: Fix up extended mode TLB for SH-X2+ cores.

2007-09-21T02:57:55Z

The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot, correspondingly, the PGD also has to be 64-bits, so fix that up. The kernel and user permission bits really are decoupled in early cuts of the silicon, which means that we also have to set corresponding kernel permissions on user pages or we end up with user pages that the kernel simply can't touch (!). Finally, with those things corrected, really enable MMUCR.ME and correct the PTEA value (this simply needs to be the upper 32-bits of the PTE, with the size and protection bit encoding). Signed-off-by: Paul Mundt