<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/include/asm-x86/cacheflush.h, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/include/asm-x86/cacheflush.h?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/include/asm-x86/cacheflush.h?h=stable'/>
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<updated>2008-10-23T05:55:20Z</updated>
<entry>
<title>x86, um: ... and asm-x86 move</title>
<updated>2008-10-23T05:55:20Z</updated>
<author>
<name>Al Viro</name>
<email>viro@zeniv.linux.org.uk</email>
</author>
<published>2008-08-18T01:05:42Z</published>
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<id>urn:sha1:bb8985586b7a906e116db835c64773b7a7d51663</id>
<content type='text'>
Signed-off-by: Al Viro &lt;viro@zeniv.linux.org.uk&gt;
Signed-off-by: H. Peter Anvin &lt;hpa@zytor.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'linus' into x86/pat2</title>
<updated>2008-10-10T17:30:08Z</updated>
<author>
<name>Ingo Molnar</name>
<email>mingo@elte.hu</email>
</author>
<published>2008-10-10T17:30:08Z</published>
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<id>urn:sha1:3dd392a407d15250a501fa109cc1f93fee95ef85</id>
<content type='text'>
Conflicts:
	arch/x86/mm/init_64.c
</content>
</entry>
<entry>
<title>x86: track memtype for RAM in page struct</title>
<updated>2008-10-10T17:29:18Z</updated>
<author>
<name>Suresh Siddha</name>
<email>suresh.b.siddha@intel.com</email>
</author>
<published>2008-09-24T15:53:33Z</published>
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<id>urn:sha1:9542ada803198e6eba29d3289abb39ea82047b92</id>
<content type='text'>
Track the memtype for RAM pages in page struct instead of using the
memtype list. This avoids the explosion in the number of entries in
memtype list (of the order of 20,000 with AGP) and makes the PAT
tracking simpler.

We are using PG_arch_1 bit in page-&gt;flags.

We still use the memtype list for non RAM pages.

Signed-off-by: Suresh Siddha &lt;suresh.b.siddha@intel.com&gt;
Signed-off-by: Venkatesh Pallipadi &lt;venkatesh.pallipadi@intel.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>x86, cpa: remove cpa pool code</title>
<updated>2008-10-10T17:29:16Z</updated>
<author>
<name>Suresh Siddha</name>
<email>suresh.b.siddha@intel.com</email>
</author>
<published>2008-09-23T21:00:41Z</published>
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<id>urn:sha1:8311eb84bf842d345f543f4c62ca2b6ea26f638c</id>
<content type='text'>
Interrupt context no longer splits large page in cpa(). So we can do away
with cpa memory pool code.

Signed-off-by: Suresh Siddha &lt;suresh.b.siddha@intel.com&gt;
Cc: Suresh Siddha &lt;suresh.b.siddha@intel.com&gt;
Cc: arjan@linux.intel.com
Cc: venkatesh.pallipadi@intel.com
Cc: jeremy@goop.org
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>x86, pageattr: introduce APIs to change pageattr of a page array</title>
<updated>2008-08-21T11:47:45Z</updated>
<author>
<name>Shaohua Li</name>
<email>shaohua.li@intel.com</email>
</author>
<published>2008-08-21T02:46:06Z</published>
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<id>urn:sha1:d75586ad01e6c5a30e7337fb87d61e03556a1ecb</id>
<content type='text'>
Add array interface APIs of pageattr. page based cache flush is quite
slow for a lot of pages. If pages are more than 1024 (4M), the patch
will use a wbinvd(). We have a simple test here (run a 3d game - open
arena), nearly all agp memory allocation are small (&lt; 1M), so suppose
this will not impact runtime performance.

Signed-off-by: Dave Airlie &lt;airlied@gmail.com&gt;
Signed-off-by: Shaohua Li &lt;shaohua.li@intel.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>Revert "introduce two APIs for page attribute"</title>
<updated>2008-08-21T11:46:33Z</updated>
<author>
<name>Ingo Molnar</name>
<email>mingo@elte.hu</email>
</author>
<published>2008-08-21T11:46:33Z</published>
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<id>urn:sha1:cacf890694a36124ceddce44ff4c7b02d372ce7c</id>
<content type='text'>
This reverts commit 1ac2f7d55b7ee1613c90631e87fea22ec06781e5.
</content>
</entry>
<entry>
<title>introduce two APIs for page attribute</title>
<updated>2008-08-15T14:30:45Z</updated>
<author>
<name>Shaohua Li</name>
<email>shaohua.li@intel.com</email>
</author>
<published>2008-08-04T06:51:24Z</published>
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<id>urn:sha1:1ac2f7d55b7ee1613c90631e87fea22ec06781e5</id>
<content type='text'>
Introduce two APIs for page attribute. flushing tlb/cache in every page
attribute is expensive. AGP gart usually will do a lot of operations to
change a page to uc, new APIs can reduce flush.

Signed-off-by: Shaohua Li &lt;shaohua.li@intel.com&gt;
Cc: airlied@linux.ie
Cc: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Cc: Arjan van de Ven &lt;arjan@infradead.org&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>x86: consolidate header guards</title>
<updated>2008-07-22T19:31:34Z</updated>
<author>
<name>Vegard Nossum</name>
<email>vegard.nossum@gmail.com</email>
</author>
<published>2008-06-18T15:08:48Z</published>
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<id>urn:sha1:77ef50a522717fa040636ee1017179ceba12ff62</id>
<content type='text'>
This patch is the result of an automatic script that consolidates the
format of all the headers in include/asm-x86/.

The format:

1. No leading underscore. Names with leading underscores are reserved.
2. Pathname components are separated by two underscores. So we can
   distinguish between mm_types.h and mm/types.h.
3. Everything except letters and numbers are turned into single
   underscores.

Signed-off-by: Vegard Nossum &lt;vegard.nossum@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: add comments to describe the new api's in cacheflush.h</title>
<updated>2008-04-17T15:41:31Z</updated>
<author>
<name>Arjan van de Ven</name>
<email>arjan@linux.intel.com</email>
</author>
<published>2008-04-17T15:41:31Z</published>
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<id>urn:sha1:7219bebd72726c13c1eaaa3ade0e829e998fb3b1</id>
<content type='text'>
The new cacheflush.h API's didn't have any comments describing
how they're to be used yet and the conventions around these functions.
This patch adds comments to this effect; in order for that to be
a logical series, some prototypes had to move around.

Signed-off-by: Arjan van de Ven &lt;arjan@linux.intel.com&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
<entry>
<title>x86: add set_memory_4k to pageattr.c</title>
<updated>2008-04-17T15:41:30Z</updated>
<author>
<name>Andi Kleen</name>
<email>andi@firstfloor.org</email>
</author>
<published>2008-03-12T02:53:29Z</published>
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<id>urn:sha1:c9caa02c529d5e113e40cbc77254558fcdfa4215</id>
<content type='text'>
Add a new function to force split large pages into 4k pages.
This is needed for some followup optimizations.

I had to add a new field to cpa_data to pass down the information
that try_preserve_large_page should not run.

Right now no set_page_4k() because I didn't need it and all the
specialized users I have in mind would be more comfortable with
pure addresses. I also didn't export it because it's unlikely
external code needs it.

Signed-off-by: Andi Kleen &lt;ak@suse.de&gt;
Cc: andreas.herrmann3@amd.com
Cc: mingo@elte.hu
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Ingo Molnar &lt;mingo@elte.hu&gt;
</content>
</entry>
</feed>
