<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/include/linux/clk/qcom.h, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/include/linux/clk/qcom.h?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/include/linux/clk/qcom.h?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2026-07-23T19:13:51Z</updated>
<entry>
<title>clk: qcom: Add generic clkref_en support</title>
<updated>2026-07-23T19:13:51Z</updated>
<author>
<name>Qiang Yu</name>
<email>qiang.yu@oss.qualcomm.com</email>
</author>
<published>2026-07-22T05:58:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=22c70e5732005356a4bc2601e7dcf878aab101e0'/>
<id>urn:sha1:22c70e5732005356a4bc2601e7dcf878aab101e0</id>
<content type='text'>
Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through
a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en
register controls whether refclk is gated through to the PHY side.

These clkref controls are different from typical GCC branch clocks:
- only a single enable bit is present, without branch-style config bits
- regulators must be voted before enable and unvoted after disable

Model this as a dedicated clk_ref clock type with custom clk_ops instead
of reusing struct clk_branch semantics.

Also provide a common registration/probe API so the same clkref model
can be reused regardless of where clkref_en registers are placed, e.g.
TCSR on glymur and TLMM on SM8750.

Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Signed-off-by: Qiang Yu &lt;qiang.yu@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260721-tcsr_qre_0721-v10-3-d2fa68c63b78@oss.qualcomm.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
</entry>
</feed>
