wireguard-linux/sound/soc/sof/intel/byt.c, branch jd/unified-crypt-queue

ASoC: SOF: Intel: add namespace for XTENSA

2019-12-18T20:02:21Z

Now that Xtensa stuff is only referenced in Intel stuff, define namespace and import it in Intel BYT/BDW/HDaudio modules Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191217202231.18259-9-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: move arch_ops under ops

2019-12-18T20:02:02Z

The current structures are not well designed. We include Xtensa information from the ACPI and PCI levels, but at the Kconfig/module level everything Xtensa related is included at the sof/intel level. Move the arch_ops under ops so that Xtensa is hidden in the DSP ops, with a structure that follows the Kconfig/module partition. Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191217202231.18259-8-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: add namespaces for BAYTRAIL and MERRIFIELD

2019-12-18T19:51:02Z

Define separate namespaces and include them in ACPI and PCI top-level modules. Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191217202231.18259-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: add module namespace for legacy IPC

2019-12-18T19:50:53Z

The legacy IPC routines are only used by broadwell and baytrail modules, import them as needed and make sure other modules cannot load them. Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191217202231.18259-2-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

Merge branch 'for-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-5.6

2019-12-10T13:27:14Z

ASoC: SOF: Intel: byt: fixup topology filename for BYT-CR

2019-12-10T13:20:08Z

On Baytrail-CR, SSP0 needs to be used instead of SSP2. The substitution is assumed to be done in the topology file. When Baytrail-CR is detected, add -ssp0 suffix to the topology file name so that the topology code picks up the correct file. Tested on Asus T100TAF Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191210004854.16845-8-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: split cht and byt debug window sizes

2019-12-10T13:11:38Z

Turns out SSP 3-5 are only available on cht, to avoid dumping on undefined registers let's split the definition. Signed-off-by: Curtis Malainey Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191210004854.16845-7-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Make creation of machine device from SOF core optional

2019-12-09T18:39:35Z

Currently, SOF probes machine drivers by creating a platform device and passing the machine description as private data. This is driven by the ACPI restrictions. Ideally, ACPI tables should contain the description for the machine driver. This is not possible because ACPI tables are frozen and used on multiple OS-es (e.g Windows). In the case of Device Tree we don't have this restriction, so we choose to probe the machine drivers by creating a DT node as is the standard ALSA way. This patch makes the probing of machine drivers from SOF core optional allowing for Device Tree platforms to decouple the SOF core from machine driver probing. Along with this, it also consolidates the machine driver selection for Intel platforms by defining optional ops for selecting the machine driver based on the ACPI match for HDA and non-HDA platforms and setting the mach params. Signed-off-by: Daniel Baluta Signed-off-by: Ranjani Sridharan Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191204211556.12671-11-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: BYT: fix a copy/paste mistake in byt_dump()

2019-11-27T12:50:28Z

The shim registers in BYT/CHT/BSW are 64bits based, correct the copy/paste (from bdw.c where the shim registers are 32bits based) error in byt_dump(). Fixes: 3a9e204d4e36 ("ASoC: SOF: Intel: Add context data to any IPC timeout") Signed-off-by: Keyon Jie Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191126141533.21601-1-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: only support INFO_BATCH for legacy platforms

2019-10-25T10:08:04Z

The current position update is not precise enough for PulseAudio to work reliably with the timer-based scheduling on Baytrail, Cherrytrail, Broadwell. Disable the NO_PERIOD_WAKEUP capability and use BATCH to signal that the position is only reliable and updated during period_elapsed events. This will be reverted when the firmware provides a more accurate position for those platforms. Reviewed-by: Jaska Uimonen Reviewed-by: Ranjani Sridharan Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191024210318.30068-3-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown