wireguard-linux/sound/soc/sof/intel/cnl.c, branch jd/orphan-parallel

ASoC: SOF: Intel: remove the HDA_DSP_CORE_MASK() macro

2020-09-11T14:29:31Z

Remove the HDA_DSP_CORE_MASK() macro and use BIT() and GENMASK() macros directly for more clarity. Signed-off-by: Ranjani Sridharan Reviewed-by: Rander Wang Reviewed-by: Guennadi Liakhovetski Reviewed-by: Keyon Jie Reviewed-by: Pierre-Louis Bossart Signed-off-by: Kai Vehmanen Link: https://lore.kernel.org/r/20200910164125.2033062-4-kai.vehmanen@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: rename cores_mask to host_managed_cores_mask

2020-09-11T14:29:29Z

Rename the cores_mask in struct sof_intel_dsp_desc to host_managed_cores_mask to be more indicative of the fact that only these cores can be powered up/down by the host. Signed-off-by: Ranjani Sridharan Reviewed-by: Rander Wang Reviewed-by: Guennadi Liakhovetski Reviewed-by: Keyon Jie Reviewed-by: Pierre-Louis Bossart Signed-off-by: Kai Vehmanen Link: https://lore.kernel.org/r/20200910164125.2033062-2-kai.vehmanen@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: hda: Add sof_tgl_ops for TGL platforms

2020-08-27T13:22:23Z

Separate the dsp ops for TGL ops to specify the use of ICCMAX FW boot sequence in the run op. All other ops are identical. Also separate the TGL descriptors into a separate file to make it easier to follow. Reviewed-by: Guennadi Liakhovetski Reviewed-by: Pierre-Louis Bossart Signed-off-by: Ranjani Sridharan Link: https://lore.kernel.org/r/20200826184532.1612070-8-ranjani.sridharan@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: delete repeated words in comments

2020-08-18T13:52:42Z

Drop the repeated words {that, the} in comments. Signed-off-by: Randy Dunlap Acked-by: Pierre-Louis Bossart Cc: Liam Girdwood Cc: Mark Brown Cc: alsa-devel@alsa-project.org Link: https://lore.kernel.org/r/20200808012156.10827-1-rdunlap@infradead.org Signed-off-by: Mark Brown

ASoC: SOF/Intel: clarify SPDX license with GPL-2.0-only

2020-05-01T16:45:24Z

Remove the ambiguity with GPL-2.0 and use an explicit GPL-2.0-only tag. Signed-off-by: Pierre-Louis Bossart Reviewed-by: Daniel Baluta Reviewed-by: Kai Vehmanen Reviewed-by: Guennadi Liakhovetski Link: https://lore.kernel.org/r/20200501145850.15178-1-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: remove unnecessary waitq before loading firmware

2020-03-13T15:13:25Z

The HDA_DSP_IPC_PURGE_FW IPC from ROM is already handled in cl_dsp_init(), and it will never be received in the IRQ thread, so the wait condition on this IPC will never be satisfied. The wait before loading firmware is redundant and can be removed safely. Signed-off-by: Amery Song Signed-off-by: Pierre-Louis Bossart Reviewed-by: Keyon Jie Reviewed-by: Kai Vehmanen Reviewed-by: Pierre Bossart Reviewed-by: Ranjani Sridharan Reviewed-by: Guennadi Liakhovetski Link: https://lore.kernel.org/r/20200312200622.24477-6-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: Probe compress operations

2020-02-18T21:52:09Z

Add HDA handlers for soc_compr_ops and snd_compr_ops which cover probe related operations. Implementation supports both connection purposes. These merely define stream setups as core flow is covered by SOF compress core. Signed-off-by: Cezary Rojewski Acked-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20200218143924.10565-8-cezary.rojewski@intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: cnl: Implement feature to support DSP D0i3 in S0

2020-02-11T11:48:07Z

This patch implements support for DSP D0i3 when the system is in S0. The basic idea is to schedule a delayed work after every successful IPC TX that checks if there are only D0I3-compatible streams active and if so transition the DSP to D0I3. With the introduction of DSP D0I3 in S0, we need to ensure that the DSP is in D0I0 before sending any new IPCs. The exception for this would be the compact IPCs that are used to set the DSP in D0I3/D0I0 states. Signed-off-by: Keyon Jie Signed-off-by: Ranjani Sridharan Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20200129220726.31792-9-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: move arch_ops under ops

2019-12-18T20:02:02Z

The current structures are not well designed. We include Xtensa information from the ACPI and PCI levels, but at the Kconfig/module level everything Xtensa related is included at the sof/intel level. Move the arch_ops under ops so that Xtensa is hidden in the DSP ops, with a structure that follows the Kconfig/module partition. Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191217202231.18259-8-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown

ASoC: SOF: Intel: add namespace for HDA_COMMON

2019-12-18T19:52:01Z

Define namespace and include it in PCI top-level module. Signed-off-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20191217202231.18259-6-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown