<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/sound/soc/sof/intel/hda-ipc.c, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/sound/soc/sof/intel/hda-ipc.c?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/sound/soc/sof/intel/hda-ipc.c?h=jd%2Forphan-parallel'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-05-01T16:45:24Z</updated>
<entry>
<title>ASoC: SOF/Intel: clarify SPDX license with GPL-2.0-only</title>
<updated>2020-05-01T16:45:24Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2020-05-01T14:58:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e149ca29f3994ca79e9e77aa2f5b2e871e9f7c99'/>
<id>urn:sha1:e149ca29f3994ca79e9e77aa2f5b2e871e9f7c99</id>
<content type='text'>
Remove the ambiguity with GPL-2.0 and use an explicit GPL-2.0-only
tag.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Daniel Baluta &lt;daniel.baluta@nxp.com&gt;
Reviewed-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Reviewed-by: Guennadi Liakhovetski &lt;guennadi.liakhovetski@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200501145850.15178-1-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: remove unnecessary waitq before loading firmware</title>
<updated>2020-03-13T15:13:25Z</updated>
<author>
<name>Amery Song</name>
<email>chao.song@intel.com</email>
</author>
<published>2020-03-12T20:06:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=828c2f7871d8f8051c7f412c74115ef2c583b1ce'/>
<id>urn:sha1:828c2f7871d8f8051c7f412c74115ef2c583b1ce</id>
<content type='text'>
The HDA_DSP_IPC_PURGE_FW IPC from ROM is already handled in
cl_dsp_init(), and it will never be received in the IRQ thread,
so the wait condition on this IPC will never be satisfied. The
wait before loading firmware is redundant and can be removed safely.

Signed-off-by: Amery Song &lt;chao.song@intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Keyon Jie &lt;yang.jie@linux.intel.com&gt;
Reviewed-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Reviewed-by: Pierre Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Reviewed-by: Guennadi Liakhovetski &lt;guennadi.liakhovetski@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200312200622.24477-6-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda: remove unnecessary ROM IPC filter function</title>
<updated>2020-03-13T15:13:24Z</updated>
<author>
<name>Amery Song</name>
<email>chao.song@intel.com</email>
</author>
<published>2020-03-12T20:06:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9b65b2a80e700c0dbc5c554d198e50a9e798a6d0'/>
<id>urn:sha1:9b65b2a80e700c0dbc5c554d198e50a9e798a6d0</id>
<content type='text'>
The HDA_DSP_IPC_PURGE_FW IPC from ROM is already handled in
cl_dsp_init(), and as IPC IRQ is disabled at this stage, this
IPC will be never received in the IRQ thread. The function
hda_dsp_ipc_is_sof for filtering the ROM IPC can be removed
safely.

Signed-off-by: Amery Song &lt;chao.song@intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Reviewed-by: Keyon &lt;yang.jie@intel.com&gt;
Reviewed-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200312200622.24477-5-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Implement Probe IPC API</title>
<updated>2020-02-18T21:52:06Z</updated>
<author>
<name>Cezary Rojewski</name>
<email>cezary.rojewski@intel.com</email>
</author>
<published>2020-02-18T14:39:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f3b433e4699fa358ce5b7bd7688bebe36068c199'/>
<id>urn:sha1:f3b433e4699fa358ce5b7bd7688bebe36068c199</id>
<content type='text'>
Add all required types and methods to support each and every request
that driver could sent to firmware. Probe is one of SOF firmware
features which allows for data extraction and injection directly from
or to DMA stream.

Exposes eight IPCs:
- addition and removal of injection DMAs
- addition and removal of probe points
- info retrieval of injection DMAs and probe points
- probe initialization and cleanup

Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Acked-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200218143924.10565-5-cezary.rojewski@intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda: solve MSI issues by merging ipc and stream irq handlers</title>
<updated>2019-12-09T18:35:56Z</updated>
<author>
<name>Bard Liao</name>
<email>yung-chuan.liao@linux.intel.com</email>
</author>
<published>2019-12-04T21:28:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7c11af9fcdc425b80f140a218d4fef9f17734bfc'/>
<id>urn:sha1:7c11af9fcdc425b80f140a218d4fef9f17734bfc</id>
<content type='text'>
The existing code uses two handlers for a shared edge-based MSI interrupts.
In corner cases, interrupts are lost, leading to IPC timeouts. Those
timeouts do not appear in legacy mode.

This patch merges the two handlers and threads into a single one, and
simplifies the mask/unmask operations by using a single top-level mask
(Global Interrupt Enable). The handler only checks for interrupt
sources using the Global Interrupt Status (GIS) field, and all the
actual work happens in the thread. This also enables us to remove the
use of spin locks. Stream events are prioritized over IPC ones.

This patch was tested with HDaudio and SoundWire platforms, and all
known IPC timeout issues are solved in MSI mode. The
SoundWire-specific patches will be provided in follow-up patches,
where the SoundWire interrupts are handled in the same thread as IPC
and stream interrupts.

Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20191204212859.13239-1-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda-ipc: Don't read mailbox for PM_GATE reply</title>
<updated>2019-10-28T14:43:49Z</updated>
<author>
<name>Keyon Jie</name>
<email>yang.jie@linux.intel.com</email>
</author>
<published>2019-10-25T22:41:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=463fbf6dc03aff41e973602bbad6cb135fa6d48a'/>
<id>urn:sha1:463fbf6dc03aff41e973602bbad6cb135fa6d48a</id>
<content type='text'>
Memory windows could be powered off before receiving PM_GATE IPC reply
from FW, we can't read the mailbox to get reply.

Signed-off-by: Keyon Jie &lt;yang.jie@linux.intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20191025224122.7718-15-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda: Use generic function for fw ready / mem windows creation</title>
<updated>2019-08-09T12:25:22Z</updated>
<author>
<name>Daniel Baluta</name>
<email>daniel.baluta@nxp.com</email>
</author>
<published>2019-08-07T15:02:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=6eebd3907527764618ee250e1106b9e809c46143'/>
<id>urn:sha1:6eebd3907527764618ee250e1106b9e809c46143</id>
<content type='text'>
We can use generic sof_fw_ready function and reduce code duplication.
Careful here that we need to provide the implementation for
get_mailbox_offset and get_window_offset.

Signed-off-by: Daniel Baluta &lt;daniel.baluta@nxp.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20190807150203.26359-7-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda: remove misleading error trace from IRQ thread</title>
<updated>2019-07-23T11:16:53Z</updated>
<author>
<name>Kai Vehmanen</name>
<email>kai.vehmanen@linux.intel.com</email>
</author>
<published>2019-07-22T14:14:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=717dedb1dcee92788b81233aa0a221573c95daff'/>
<id>urn:sha1:717dedb1dcee92788b81233aa0a221573c95daff</id>
<content type='text'>
Downgrade "nothing to do in IRQ thread" message from error to a debug
message in the IPC interrupt handler thread.

The spurious wake-up can happen if a HDA stream interrupt is
raised while the IPC interrupt thread is running. IPC functionality
is not impacted by this condition, so debug is a more appropriate
trace level.

Signed-off-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20190722141402.7194-21-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: ipc: don't check for HIPCCTL register value</title>
<updated>2019-06-03T16:49:17Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2019-06-03T16:20:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=09a173a63fbb89762712a4ec48722ba98d4e1bcc'/>
<id>urn:sha1:09a173a63fbb89762712a4ec48722ba98d4e1bcc</id>
<content type='text'>
The HIPCCTL register controls the IPC interrupts. It can be set or
cleared to mask or enable these interrupts, but it makes no sense to
read and test its fields in an interrupt (which can only executed if
its fields are set).

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda-ipc: re-enable IPC IRQ at end of handler</title>
<updated>2019-06-03T16:49:00Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2019-06-03T16:20:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=66e65339b824a597a8c750ddf993af17c847dce6'/>
<id>urn:sha1:66e65339b824a597a8c750ddf993af17c847dce6</id>
<content type='text'>
Align with Skylake driver and enable the IRQ at end of handler,
instead of at beginning.

Also add an error log if we have nothing to do in this handler.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
</feed>
