<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/sound/soc/sof/intel/hda.h, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/sound/soc/sof/intel/hda.h?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/sound/soc/sof/intel/hda.h?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-03-27T15:16:36Z</updated>
<entry>
<title>Asoc: SOF: Intel: hda: check SoundWire wakeen interrupt in irq thread</title>
<updated>2020-03-27T15:16:36Z</updated>
<author>
<name>Rander Wang</name>
<email>rander.wang@intel.com</email>
</author>
<published>2020-03-25T21:50:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=90de3281c86ae5378e951e84c76c4759390ff34d'/>
<id>urn:sha1:90de3281c86ae5378e951e84c76c4759390ff34d</id>
<content type='text'>
If pci device is in D0, wakeen interrupt will be
aggregated at cAVS level as interrupt. This commit
check the wakeen status and process it in irq thread

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Rander Wang &lt;rander.wang@intel.com&gt;
Link: https://lore.kernel.org/r/20200325215027.28716-11-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda: add WAKEEN interrupt support for SoundWire</title>
<updated>2020-03-27T15:16:35Z</updated>
<author>
<name>Rander Wang</name>
<email>rander.wang@intel.com</email>
</author>
<published>2020-03-25T21:50:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=bbd19cdca8279cf244a301c6a13ae5ec9e4ef976'/>
<id>urn:sha1:bbd19cdca8279cf244a301c6a13ae5ec9e4ef976</id>
<content type='text'>
When a SoundWire link is in clock stop state, a Slave device may wake
up the Master for some events such as jack detection. The WAKEEN
interrupt will be triggered and processed by the audio pci device.

If audio device is in D3, the interrupt will be routed to PME, or
aggregated at cAVS level as interrupt when audio device is in D0. This
patch only supports D3 case, where the audio pci device will be
resumed by a PME event and the WAKEEN interrupt will be processed
after audio pci device is powered up and ROM is initialized
successfully.

The WAKEEN handling is only enabled after the first boot due to
dependencies on a shim_lock mutex being initialized.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Rander Wang &lt;rander.wang@intel.com&gt;
Link: https://lore.kernel.org/r/20200325215027.28716-10-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda: merge IPC, stream and SoundWire interrupt handlers</title>
<updated>2020-03-27T15:16:33Z</updated>
<author>
<name>Bard Liao</name>
<email>yung-chuan.liao@linux.intel.com</email>
</author>
<published>2020-03-25T21:50:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=722ba5f1f530a919d28a0dd9e8e0ec63af18270d'/>
<id>urn:sha1:722ba5f1f530a919d28a0dd9e8e0ec63af18270d</id>
<content type='text'>
We have a single irq handler for SOF interrupts. We can further merge
SoundWire ones to completely remove MSI interrupts handling issues
leading to timeouts.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Bard Liao &lt;yung-chuan.liao@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200325215027.28716-8-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: add SoundWire configuration interface</title>
<updated>2020-03-27T15:16:29Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2020-03-25T21:50:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=51dfed1e178a38202960b98f6e29df009a06050f'/>
<id>urn:sha1:51dfed1e178a38202960b98f6e29df009a06050f</id>
<content type='text'>
Now that the SoundWire core supports the multi-step initialization,
call the relevant APIs.

The actual hardware enablement can be done in two places, ideally we'd
want to startup the SoundWire IP as soon as possible (while still
taking power rail dependencies into account)

However when suspend/resume is implemented, the DSP device will be
resumed first, and only when the DSP firmware is downloaded/booted
would the SoundWire child devices be resumed, so there are only
marginal benefits in starting the IP earlier for the first probe.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200325215027.28716-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: remove unnecessary waitq before loading firmware</title>
<updated>2020-03-13T15:13:25Z</updated>
<author>
<name>Amery Song</name>
<email>chao.song@intel.com</email>
</author>
<published>2020-03-12T20:06:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=828c2f7871d8f8051c7f412c74115ef2c583b1ce'/>
<id>urn:sha1:828c2f7871d8f8051c7f412c74115ef2c583b1ce</id>
<content type='text'>
The HDA_DSP_IPC_PURGE_FW IPC from ROM is already handled in
cl_dsp_init(), and it will never be received in the IRQ thread,
so the wait condition on this IPC will never be satisfied. The
wait before loading firmware is redundant and can be removed safely.

Signed-off-by: Amery Song &lt;chao.song@intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Keyon Jie &lt;yang.jie@linux.intel.com&gt;
Reviewed-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Reviewed-by: Pierre Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Reviewed-by: Guennadi Liakhovetski &lt;guennadi.liakhovetski@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200312200622.24477-6-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: Add Probe compress CPU DAIs</title>
<updated>2020-02-18T21:52:11Z</updated>
<author>
<name>Cezary Rojewski</name>
<email>cezary.rojewski@intel.com</email>
</author>
<published>2020-02-18T14:39:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=70368106467cd8c420176bf3ab0acc797f6584bf'/>
<id>urn:sha1:70368106467cd8c420176bf3ab0acc797f6584bf</id>
<content type='text'>
Declare extraction CPU DAI as well as sof_probe_compr_ops. FE DAIs can
link against these new CPU DAI to create new compress devices.

Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Acked-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200218143924.10565-10-cezary.rojewski@intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: Probe compress operations</title>
<updated>2020-02-18T21:52:09Z</updated>
<author>
<name>Cezary Rojewski</name>
<email>cezary.rojewski@intel.com</email>
</author>
<published>2020-02-18T14:39:22Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=4c414da93a4642d02c67fbe82f1834be7bf586b7'/>
<id>urn:sha1:4c414da93a4642d02c67fbe82f1834be7bf586b7</id>
<content type='text'>
Add HDA handlers for soc_compr_ops and snd_compr_ops which cover probe
related operations. Implementation supports both connection purposes.
These merely define stream setups as core flow is covered by SOF
compress core.

Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Acked-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200218143924.10565-8-cezary.rojewski@intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: Expose SDnFMT helpers</title>
<updated>2020-02-18T21:52:08Z</updated>
<author>
<name>Cezary Rojewski</name>
<email>cezary.rojewski@intel.com</email>
</author>
<published>2020-02-18T14:39:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=49d7948ed174cc170041bf3d22e1f085fd8b87f0'/>
<id>urn:sha1:49d7948ed174cc170041bf3d22e1f085fd8b87f0</id>
<content type='text'>
Hda stream is setup in similar fashion for compress as it is for pcm
operations. To reuse existing code in compress path, expose SDnFMT
helper routines.

Signed-off-by: Cezary Rojewski &lt;cezary.rojewski@intel.com&gt;
Acked-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200218143924.10565-7-cezary.rojewski@intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: cnl: Implement feature to support DSP D0i3 in S0</title>
<updated>2020-02-11T11:48:07Z</updated>
<author>
<name>Ranjani Sridharan</name>
<email>ranjani.sridharan@linux.intel.com</email>
</author>
<published>2020-01-29T22:07:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=63e51fd33fef04b634a0c32ae491ab16a19cb17c'/>
<id>urn:sha1:63e51fd33fef04b634a0c32ae491ab16a19cb17c</id>
<content type='text'>
This patch implements support for DSP D0i3 when the system
is in S0. The basic idea is to schedule a delayed work after
every successful IPC TX that checks if there are only
D0I3-compatible streams active and if so transition
the DSP to D0I3.

With the introduction of DSP D0I3 in S0, we need to
ensure that the DSP is in D0I0 before sending any new
IPCs. The exception for this would be the
compact IPCs that are used to set the DSP in
D0I3/D0I0 states.

Signed-off-by: Keyon Jie &lt;yang.jie@linux.intel.com&gt;
Signed-off-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200129220726.31792-9-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Move DSP power state transitions to platform-specific ops</title>
<updated>2020-02-11T11:48:05Z</updated>
<author>
<name>Ranjani Sridharan</name>
<email>ranjani.sridharan@linux.intel.com</email>
</author>
<published>2020-01-29T22:07:22Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=61e285caf40fef18e8bd7cea5237ee6723609a1c'/>
<id>urn:sha1:61e285caf40fef18e8bd7cea5237ee6723609a1c</id>
<content type='text'>
The DSP device substates such as D0I0/D0I3
are platform-specific. Therefore, the d0_substate
field of struct snd_sof_dev is replaced
with the dsp_power_state field which represents the current
state of the DSP. This field holds both the device state
and the platform-specific substate values.

With the DSP device substates being platform-specific,
the DSP power state transitions need to be performed in
the platform-specific suspend/resume ops as well.

In order to achieve this, the ops signature has to be
modified to pass the target device state as an
argument. The target substate will be determined by
the platform-specific ops before performing the transition.
For example, in the case of the system suspending to S0IX,
the top-level SOF device suspend callback needs to
only determine if the DSP will be entering
D3 or remain in D0. The target substate in case the device
needs to remain in D0 (D0I0 or D0I3) will be determined
by the platform-specific suspend op.

With the addition of the extended set of power states for the DSP,
the set_power_state op for HDA platforms has to be extended
to handle only the appropriate state transitions. So, the
implementation for the Intel HDA platforms is also modified.

Signed-off-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200129220726.31792-6-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
</feed>
