<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/sound/soc/sof/intel/shim.h, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/sound/soc/sof/intel/shim.h?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/sound/soc/sof/intel/shim.h?h=jd%2Forphan-parallel'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-09-11T14:29:29Z</updated>
<entry>
<title>ASoC: SOF: rename cores_mask to host_managed_cores_mask</title>
<updated>2020-09-11T14:29:29Z</updated>
<author>
<name>Ranjani Sridharan</name>
<email>ranjani.sridharan@linux.intel.com</email>
</author>
<published>2020-09-10T16:41:22Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=64b969177c744a76142f45823dd9d94c38f79cd0'/>
<id>urn:sha1:64b969177c744a76142f45823dd9d94c38f79cd0</id>
<content type='text'>
Rename the cores_mask in struct sof_intel_dsp_desc to
host_managed_cores_mask to be more indicative of the fact that
only these cores can be powered up/down by the host.

Signed-off-by: Ranjani Sridharan &lt;ranjani.sridharan@linux.intel.com&gt;
Reviewed-by: Rander Wang &lt;rander.wang@linux.intel.com&gt;
Reviewed-by: Guennadi Liakhovetski &lt;guennadi.liakhovetski@linux.intel.com&gt;
Reviewed-by: Keyon Jie &lt;yang.jie@linux.intel.com&gt;
Reviewed-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200910164125.2033062-2-kai.vehmanen@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF/Intel: clarify SPDX license with GPL-2.0-only</title>
<updated>2020-05-01T16:45:24Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2020-05-01T14:58:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e149ca29f3994ca79e9e77aa2f5b2e871e9f7c99'/>
<id>urn:sha1:e149ca29f3994ca79e9e77aa2f5b2e871e9f7c99</id>
<content type='text'>
Remove the ambiguity with GPL-2.0 and use an explicit GPL-2.0-only
tag.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Daniel Baluta &lt;daniel.baluta@nxp.com&gt;
Reviewed-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Reviewed-by: Guennadi Liakhovetski &lt;guennadi.liakhovetski@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200501145850.15178-1-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: remove references to Haswell</title>
<updated>2019-12-18T19:51:40Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2019-12-17T20:22:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1fa44098b683312b426bd05f1bfc0b5b1fa7860a'/>
<id>urn:sha1:1fa44098b683312b426bd05f1bfc0b5b1fa7860a</id>
<content type='text'>
There are no known commercial devices using Haswell, and there is no
support for Haswell in SOF so remove remaining definitions and
structures.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20191217202231.18259-5-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: hda: add SSP info to the chip info struct</title>
<updated>2019-05-03T05:57:39Z</updated>
<author>
<name>Zhu Yingjiang</name>
<email>yingjiang.zhu@linux.intel.com</email>
</author>
<published>2019-04-30T23:09:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b095fe47bc1e1c3bf114fde7b76a387ee7b16934'/>
<id>urn:sha1:b095fe47bc1e1c3bf114fde7b76a387ee7b16934</id>
<content type='text'>
add SSP info of APL and CNL, to the sof_intel_dsp_desc
structure. The max SSP count the platform support and
the SSP base address.

Signed-off-by: Zhu Yingjiang &lt;yingjiang.zhu@linux.intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: SOF: Intel: Add BYT, CHT and BSW DSP HW support.</title>
<updated>2019-04-27T17:50:33Z</updated>
<author>
<name>Liam Girdwood</name>
<email>liam.r.girdwood@linux.intel.com</email>
</author>
<published>2019-04-12T16:08:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9e42c5ca4a276a668b11116704f5f0d66ab80608'/>
<id>urn:sha1:9e42c5ca4a276a668b11116704f5f0d66ab80608</id>
<content type='text'>
Add support for the audio DSP hardware found on Intel Baytrail,
Cherrytrail and Braswell based devices.

Signed-off-by: Rander Wang &lt;rander.wang@linux.intel.com&gt;
Signed-off-by: Pan Xiuli &lt;xiuli.pan@linux.intel.com&gt;
Signed-off-by: Liam Girdwood &lt;liam.r.girdwood@linux.intel.com&gt;
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Takashi Iwai &lt;tiwai@suse.de&gt;
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
</content>
</entry>
</feed>
