<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/tools/arch/riscv/include/asm, branch update-toolchain</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/tools/arch/riscv/include/asm?h=update-toolchain</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/tools/arch/riscv/include/asm?h=update-toolchain'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2024-02-26T04:44:04Z</updated>
<entry>
<title>tools: riscv: Add header file vdso/processor.h</title>
<updated>2024-02-26T04:44:04Z</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1d50c77208933fd1c18be8359633913d9c482e5a'/>
<id>urn:sha1:1d50c77208933fd1c18be8359633913d9c482e5a</id>
<content type='text'>
Borrow the cpu_relax() definitions from kernel's
arch/riscv/include/asm/vdso/processor.h to tools/ for riscv.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>tools: riscv: Add header file csr.h</title>
<updated>2024-02-26T04:44:02Z</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a69459d579df9200bc6f58ff04e1a8a4984016a7'/>
<id>urn:sha1:a69459d579df9200bc6f58ff04e1a8a4984016a7</id>
<content type='text'>
Borrow the csr definitions and operations from kernel's
arch/riscv/include/asm/csr.h to tools/ for riscv.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
</feed>
