<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/tools/testing/selftests/resctrl/cat_test.c, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/tools/testing/selftests/resctrl/cat_test.c?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/tools/testing/selftests/resctrl/cat_test.c?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-02-11T01:43:41Z</updated>
<entry>
<title>selftests/resctrl: Disable MBA and MBM tests for AMD</title>
<updated>2020-02-11T01:43:41Z</updated>
<author>
<name>Babu Moger</name>
<email>babu.moger@amd.com</email>
</author>
<published>2020-01-16T21:32:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=85f553d24ada5399cab730e3199a970e2cc78c82'/>
<id>urn:sha1:85f553d24ada5399cab730e3199a970e2cc78c82</id>
<content type='text'>
For now, disable MBA and MBM tests for AMD. Deciding test pass/fail
is not clear right now. We can enable when we have some clarity.

Signed-off-by: Babu Moger &lt;babu.moger@amd.com&gt;
Co-developed-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>selftests/resctrl: Add Cache Allocation Technology (CAT) selftest</title>
<updated>2020-02-11T01:43:07Z</updated>
<author>
<name>Fenghua Yu</name>
<email>fenghua.yu@intel.com</email>
</author>
<published>2020-01-16T21:32:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=790bf585b0eeec9aa0e680ba090142b98da7f948'/>
<id>urn:sha1:790bf585b0eeec9aa0e680ba090142b98da7f948</id>
<content type='text'>
Cache Allocation Technology (CAT) selftest allocates a portion of
last level cache and starts a benchmark to read each cache
line in this portion of cache. Measure the cache misses in perf and
the misses should be equal to the number of cache lines in this
portion of cache.

We don't use CQM to calculate cache usage because some CAT enabled
platforms don't have CQM.

Co-developed-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Signed-off-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Co-developed-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
</content>
</entry>
</feed>
