<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/tools/testing/selftests/resctrl/resctrlfs.c, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/tools/testing/selftests/resctrl/resctrlfs.c?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/tools/testing/selftests/resctrl/resctrlfs.c?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-02-11T01:43:32Z</updated>
<entry>
<title>selftests/resctrl: Use cache index3 id for AMD schemata masks</title>
<updated>2020-02-11T01:43:32Z</updated>
<author>
<name>Babu Moger</name>
<email>babu.moger@amd.com</email>
</author>
<published>2020-01-16T21:32:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c0327e1d7c42adb31a9541de6812f740893177a1'/>
<id>urn:sha1:c0327e1d7c42adb31a9541de6812f740893177a1</id>
<content type='text'>
AMD uses the cache l3 boundary for schemata masks. Update it accordigly.

Signed-off-by: Babu Moger &lt;babu.moger@amd.com&gt;
Co-developed-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>selftests/resctrl: Add Cache Allocation Technology (CAT) selftest</title>
<updated>2020-02-11T01:43:07Z</updated>
<author>
<name>Fenghua Yu</name>
<email>fenghua.yu@intel.com</email>
</author>
<published>2020-01-16T21:32:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=790bf585b0eeec9aa0e680ba090142b98da7f948'/>
<id>urn:sha1:790bf585b0eeec9aa0e680ba090142b98da7f948</id>
<content type='text'>
Cache Allocation Technology (CAT) selftest allocates a portion of
last level cache and starts a benchmark to read each cache
line in this portion of cache. Measure the cache misses in perf and
the misses should be equal to the number of cache lines in this
portion of cache.

We don't use CQM to calculate cache usage because some CAT enabled
platforms don't have CQM.

Co-developed-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Signed-off-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Co-developed-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>selftests/resctrl: Add Cache QoS Monitoring (CQM) selftest</title>
<updated>2020-02-11T01:42:57Z</updated>
<author>
<name>Fenghua Yu</name>
<email>fenghua.yu@intel.com</email>
</author>
<published>2020-01-16T21:32:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=78941183d1b151317beb37b25690b7d87fe2596d'/>
<id>urn:sha1:78941183d1b151317beb37b25690b7d87fe2596d</id>
<content type='text'>
Cache QoS Monitoring (CQM) selftest starts stressful cache benchmark
with specified size of memory to access the cache. Last Level cache
occupancy reported by CQM should be close to the size of the memory.

Co-developed-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Signed-off-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Co-developed-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>selftests/resctrl: Add MBM test</title>
<updated>2020-02-11T01:42:29Z</updated>
<author>
<name>Fenghua Yu</name>
<email>fenghua.yu@intel.com</email>
</author>
<published>2020-01-16T21:32:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ecdbb911f22d6cc5d422571dedf048b889d71417'/>
<id>urn:sha1:ecdbb911f22d6cc5d422571dedf048b889d71417</id>
<content type='text'>
MBM (Memory Bandwidth Monitoring) test is the first implemented selftest.
It starts a stressful memory bandwidth benchmark and assigns the
bandwidth pid in a resctrl monitoring group. Read and compare perf IMC
counter and MBM total bytes for the benchmark. The numbers should be
close enough to pass the test.

Default benchmark is built-in fill_buf. But users can specify their
own benchmark by option "-b".

We can add memory bandwidth monitoring for multiple processes in the
future.

Co-developed-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Signed-off-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Co-developed-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>selftests/resctrl: Add basic resctrl file system operations and data</title>
<updated>2020-02-11T01:37:45Z</updated>
<author>
<name>Sai Praneeth Prakhya</name>
<email>sai.praneeth.prakhya@intel.com</email>
</author>
<published>2020-01-16T21:32:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=591a6e8588fc1dbdc04355e8ad7b0be43d221c9c'/>
<id>urn:sha1:591a6e8588fc1dbdc04355e8ad7b0be43d221c9c</id>
<content type='text'>
The basic resctrl file system operations and data are added for future
usage by resctrl selftest tool.

Signed-off-by: Sai Praneeth Prakhya &lt;sai.praneeth.prakhya@intel.com&gt;
Co-developed-by: Babu Moger &lt;babu.moger@amd.com&gt;
Signed-off-by: Babu Moger &lt;babu.moger@amd.com&gt;
Co-developed-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Fenghua Yu &lt;fenghua.yu@intel.com&gt;
Signed-off-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
</content>
</entry>
</feed>
