diff options
| author |   Qiang Yu <quic_qianyu@quicinc.com> | 2024-08-05 19:45:18 +0300 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2024-08-29 23:49:10 +0530 |
| commit | 00c5f32283f377ec60870bccbd518d9feb7fbc52 (patch) | |
| tree | cebca13dadeb3eae03ed7d46be88f77b5d3f542b | |
| parent | phy: airoha: adjust initialization delay in airoha_pcie_phy_init() (diff) | |
| download | wireguard-linux-00c5f32283f377ec60870bccbd518d9feb7fbc52.tar.xz wireguard-linux-00c5f32283f377ec60870bccbd518d9feb7fbc52.zip | |
phy: qcom: qmp-pcie: Configure all tables on port B PHY
Currently, only the RX and TX tables are written to the second PHY
(port B) when the 4-lanes mode is configured, but according to Qualcomm
internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need
to be written as well.
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240805-phy-qcom-qmp-pcie-write-all-tbls-second-port-v3-1-6967c6bf61d1@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 9cfc3ddf0e8a..35162345064a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3699,18 +3699,30 @@ static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_ { const struct qmp_phy_cfg *cfg = qmp->cfg; const struct qmp_pcie_offsets *offs = cfg->offsets; - void __iomem *tx3, *rx3, *tx4, *rx4; + void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd; + serdes = qmp->port_b + offs->serdes; tx3 = qmp->port_b + offs->tx; rx3 = qmp->port_b + offs->rx; tx4 = qmp->port_b + offs->tx2; rx4 = qmp->port_b + offs->rx2; + pcs = qmp->port_b + offs->pcs; + pcs_misc = qmp->port_b + offs->pcs_misc; + ln_shrd = qmp->port_b + offs->ln_shrd; + + qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); + qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); + + qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); + qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + + qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); } static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) |