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| author |   Lu Baolu <baolu.lu@linux.intel.com> | 2024-07-09 23:26:43 +0800 |
|---|---|---|
| committer |   Will Deacon <will@kernel.org> | 2024-07-10 13:06:55 +0100 |
| commit | 0a3f6b3463014b03f6ad10eacc4d1d9af75d54a1 (patch) | |
| tree | 90060f7e80b4fbe94628c8df38ad16c275c101e5 | |
| parent | iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH (diff) | |
| download | wireguard-linux-0a3f6b3463014b03f6ad10eacc4d1d9af75d54a1.tar.xz wireguard-linux-0a3f6b3463014b03f6ad10eacc4d1d9af75d54a1.zip | |
iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()
The helper calculate_psi_aligned_address() is used to convert an arbitrary
range into a size-aligned one.
The aligned_pages variable is calculated from input start and end, but is
not adjusted when the start pfn is not aligned and the mask is adjusted,
which results in an incorrect number of pages returned.
The number of pages is used by qi_flush_piotlb() to flush caches for the
first-stage translation. With the wrong number of pages, the cache is not
synchronized, leading to inconsistencies in some cases.
Fixes: c4d27ffaa8eb ("iommu/vt-d: Add cache tag invalidation helpers")
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20240709152643.28109-3-baolu.lu@linux.intel.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/iommu/intel/cache.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c index 0a3bb38a5289..44e92638c0cd 100644 --- a/drivers/iommu/intel/cache.c +++ b/drivers/iommu/intel/cache.c @@ -246,6 +246,7 @@ static unsigned long calculate_psi_aligned_address(unsigned long start, */ shared_bits = ~(pfn ^ end_pfn) & ~bitmask; mask = shared_bits ? __ffs(shared_bits) : MAX_AGAW_PFN_WIDTH; + aligned_pages = 1UL << mask; } *_pages = aligned_pages; |