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| author |   Sean Anderson <sean.anderson@linux.dev> | 2024-05-31 12:13:37 -0400 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2024-08-30 10:48:36 -0500 |
| commit | 0b93267adb34f39ca5b1574cf3766ee5fe3d44b6 (patch) | |
| tree | da294fb441698bd7fd5dd81dddddfa0d5e91ad59 | |
| parent | PCI: xilinx-nwl: Add PHY support (diff) | |
| download | wireguard-linux-0b93267adb34f39ca5b1574cf3766ee5fe3d44b6.tar.xz wireguard-linux-0b93267adb34f39ca5b1574cf3766ee5fe3d44b6.zip | |
arm64: zynqmp: Add PCIe phys property for ZCU102
Add PCIe phy bindings for the ZCU102.
Link: https://lore.kernel.org/r/20240531161337.864994-8-sean.anderson@linux.dev
Tested-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index ad8f23a0ec67..d2175f3dd099 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -941,6 +941,7 @@ &pcie { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; }; &psgtr { |