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| author |   Alexandre Courbot <acourbot@nvidia.com> | 2014-07-08 21:32:13 +0900 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2014-08-04 10:07:33 +0200 |
| commit | 0c6b1e4ba74f58ee1507d456e52c630b4b8ff174 (patch) | |
| tree | f42d3fd223684c073d705f7b957f1f716a09500b | |
| parent | drm/tegra: sor - missing unlock on error (diff) | |
| download | wireguard-linux-0c6b1e4ba74f58ee1507d456e52c630b4b8ff174.tar.xz wireguard-linux-0c6b1e4ba74f58ee1507d456e52c630b4b8ff174.zip | |
drm/tegra: dsi - Handle non-continuous clock flag
Handle the MIPI_DSI_CLOCK_NONCONTINUOUS flag and only set TX-only
clock behavior when this flag is present to allow panels requiring
continuous clock mode to operate with this driver.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/tegra/dsi.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index bd56f2affa78..eadfeaf9e1eb 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -474,7 +474,8 @@ static int tegra_output_dsi_enable(struct tegra_output *output) tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); value = tegra_dsi_readl(dsi, DSI_CONTROL); - value |= DSI_CONTROL_HS_CLK_CTRL; + if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + value |= DSI_CONTROL_HS_CLK_CTRL; value &= ~DSI_CONTROL_TX_TRIG(3); value &= ~DSI_CONTROL_DCS_ENABLE; value |= DSI_CONTROL_VIDEO_ENABLE; |