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| author |   Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> | 2024-10-28 12:30:13 -0700 |
|---|---|---|
| committer |   Matt Roper <matthew.d.roper@intel.com> | 2024-10-29 07:36:34 -0700 |
| commit | 0d94f52cece405d088849f2c42e3ffd90c197b81 (patch) | |
| tree | 8f6756b9baf5a19a25d670711f5d0d995b9677b9 | |
| parent | drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register (diff) | |
| download | wireguard-linux-0d94f52cece405d088849f2c42e3ffd90c197b81.tar.xz wireguard-linux-0d94f52cece405d088849f2c42e3ffd90c197b81.zip | |
drm/i915/xe3: Underrun recovery does not exist post Xe2
From platforms xe3 Underrun recovery does not exist
v2: improve DISPLAY_VER checking
BSpec: 68849
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Reviewed-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241028193015.3241858-8-clinton.a.taylor@intel.com
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4ea5b0ca4e93..0e6d6c8354ef 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -862,7 +862,7 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) */ if (IS_DG2(dev_priv)) tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; - else if (DISPLAY_VER(dev_priv) >= 13) + else if ((DISPLAY_VER(dev_priv) >= 13) && (DISPLAY_VER(dev_priv) < 30)) tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; /* Wa_14010547955:dg2 */ |