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| author |   John Madieu <john.madieu.xa@bp.renesas.com> | 2025-01-23 18:05:07 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-21 16:23:01 +0100 |
| commit | 13e9b03263dcdc760aa65c4298271746b180f113 (patch) | |
| tree | 0c93ff47f8c9e6c9c2c49c20020bf2a0e220aaab | |
| parent | arm64: dts: renesas: r9a08g045: Enable SYS node (diff) | |
| download | wireguard-linux-13e9b03263dcdc760aa65c4298271746b180f113.tar.xz wireguard-linux-13e9b03263dcdc760aa65c4298271746b180f113.zip | |
arm64: dts: renesas: r9a09g047: Add SYS node
Add a node for the System Controller to the RZ/G3E (R9A09G047) SoC DTSI,
as it is also required for SoC identification.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250123170508.13578-9-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 133aa3272d3a..c93aa16d0a6e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -154,6 +154,13 @@ #power-domain-cells = <0>; }; + sys: system-controller@10430000 { + compatible = "renesas,r9a09g047-sys"; + reg = <0 0x10430000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; + resets = <&cpg 0x30>; + }; + scif0: serial@11c01400 { compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; |