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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-06-17 16:54:32 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-19 10:53:52 +0200 |
| commit | 1606e81543f80fc3b1912957cf6d8fa62e40b8e5 (patch) | |
| tree | c6b406f6895ce97a3af8cae85ef9c63071188402 | |
| parent | clk: renesas: rzg2l: Avoid mixing error pointers and NULL (diff) | |
| download | wireguard-linux-1606e81543f80fc3b1912957cf6d8fa62e40b8e5.tar.xz wireguard-linux-1606e81543f80fc3b1912957cf6d8fa62e40b8e5.zip | |
clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()
Fix clock index out of range check for module clocks in
rzg2l_cpg_clk_src_twocell_get().
Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210617155432.18827-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/renesas/renesas-rzg2l-cpg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.c b/drivers/clk/renesas/renesas-rzg2l-cpg.c index 34e90ee46290..9addc9dae31a 100644 --- a/drivers/clk/renesas/renesas-rzg2l-cpg.c +++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c @@ -222,7 +222,7 @@ static struct clk case CPG_MOD: type = "module"; - if (clkidx > priv->num_mod_clks) { + if (clkidx >= priv->num_mod_clks) { dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); return ERR_PTR(-EINVAL); |