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author | 2024-10-03 15:06:41 +0800 | |
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committer | 2024-10-03 13:28:50 +0530 | |
commit | 1c758df5a83ea0c9b5055536336d8a586b5010b0 (patch) | |
tree | d541d240ff003bc8cdb2d662bf0eb52012c6b4ac | |
parent | soundwire: optimize sdw_bus structure (diff) | |
download | wireguard-linux-1c758df5a83ea0c9b5055536336d8a586b5010b0.tar.xz wireguard-linux-1c758df5a83ea0c9b5055536336d8a586b5010b0.zip |
soundwire: optimize sdw_slave_prop
move pointers first, and move booleans together.
before:
struct sdw_slave_prop {
u32 mipi_revision; /* 0 4 */
bool wake_capable; /* 4 1 */
bool test_mode_capable; /* 5 1 */
bool clk_stop_mode1; /* 6 1 */
bool simple_clk_stop_capable; /* 7 1 */
u32 clk_stop_timeout; /* 8 4 */
u32 ch_prep_timeout; /* 12 4 */
enum sdw_clk_stop_reset_behave reset_behave; /* 16 4 */
bool high_PHY_capable; /* 20 1 */
bool paging_support; /* 21 1 */
bool bank_delay_support; /* 22 1 */
/* XXX 1 byte hole, try to pack */
enum sdw_p15_behave p15_behave; /* 24 4 */
bool lane_control_support; /* 28 1 */
/* XXX 3 bytes hole, try to pack */
u32 master_count; /* 32 4 */
u32 source_ports; /* 36 4 */
u32 sink_ports; /* 40 4 */
/* XXX 4 bytes hole, try to pack */
struct sdw_dp0_prop * dp0_prop; /* 48 8 */
struct sdw_dpn_prop * src_dpn_prop; /* 56 8 */
/* --- cacheline 1 boundary (64 bytes) --- */
struct sdw_dpn_prop * sink_dpn_prop; /* 64 8 */
u8 scp_int1_mask; /* 72 1 */
/* XXX 3 bytes hole, try to pack */
u32 quirks; /* 76 4 */
bool clock_reg_supported; /* 80 1 */
bool use_domain_irq; /* 81 1 */
/* size: 88, cachelines: 2, members: 23 */
/* sum members: 71, holes: 4, sum holes: 11 */
/* padding: 6 */
/* last cacheline: 24 bytes */
};
after:
truct sdw_slave_prop {
struct sdw_dp0_prop * dp0_prop; /* 0 8 */
struct sdw_dpn_prop * src_dpn_prop; /* 8 8 */
struct sdw_dpn_prop * sink_dpn_prop; /* 16 8 */
u32 mipi_revision; /* 24 4 */
bool wake_capable; /* 28 1 */
bool test_mode_capable; /* 29 1 */
bool clk_stop_mode1; /* 30 1 */
bool simple_clk_stop_capable; /* 31 1 */
u32 clk_stop_timeout; /* 32 4 */
u32 ch_prep_timeout; /* 36 4 */
enum sdw_clk_stop_reset_behave reset_behave; /* 40 4 */
bool high_PHY_capable; /* 44 1 */
bool paging_support; /* 45 1 */
bool bank_delay_support; /* 46 1 */
bool lane_control_support; /* 47 1 */
enum sdw_p15_behave p15_behave; /* 48 4 */
u32 master_count; /* 52 4 */
u32 source_ports; /* 56 4 */
u32 sink_ports; /* 60 4 */
/* --- cacheline 1 boundary (64 bytes) --- */
u32 quirks; /* 64 4 */
u8 scp_int1_mask; /* 68 1 */
bool clock_reg_supported; /* 69 1 */
bool use_domain_irq; /* 70 1 */
/* size: 72, cachelines: 2, members: 23 */
/* padding: 1 */
/* last cacheline: 8 bytes */
};
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20241003070650.62787-6-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to '')
-rw-r--r-- | include/linux/soundwire/sdw.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index 6fcf122c1831..38db81f5bdb9 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -344,6 +344,9 @@ struct sdw_dpn_prop { /** * struct sdw_slave_prop - SoundWire Slave properties + * @dp0_prop: Data Port 0 properties + * @src_dpn_prop: Source Data Port N properties + * @sink_dpn_prop: Sink Data Port N properties * @mipi_revision: Spec version of the implementation * @wake_capable: Wake-up events are supported * @test_mode_capable: If test mode is supported @@ -360,15 +363,12 @@ struct sdw_dpn_prop { * SCP_AddrPage2 * @bank_delay_support: Slave implements bank delay/bridge support registers * SCP_BankDelay and SCP_NextFrame + * @lane_control_support: Slave supports lane control * @p15_behave: Slave behavior when the Master attempts a read to the Port15 * alias - * @lane_control_support: Slave supports lane control * @master_count: Number of Masters present on this Slave * @source_ports: Bitmap identifying source ports * @sink_ports: Bitmap identifying sink ports - * @dp0_prop: Data Port 0 properties - * @src_dpn_prop: Source Data Port N properties - * @sink_dpn_prop: Sink Data Port N properties * @scp_int1_mask: SCP_INT1_MASK desired settings * @quirks: bitmask identifying deltas from the MIPI specification * @clock_reg_supported: the Peripheral implements the clock base and scale @@ -377,6 +377,9 @@ struct sdw_dpn_prop { * @use_domain_irq: call actual IRQ handler on slave, as well as callback */ struct sdw_slave_prop { + struct sdw_dp0_prop *dp0_prop; + struct sdw_dpn_prop *src_dpn_prop; + struct sdw_dpn_prop *sink_dpn_prop; u32 mipi_revision; bool wake_capable; bool test_mode_capable; @@ -388,16 +391,13 @@ struct sdw_slave_prop { bool high_PHY_capable; bool paging_support; bool bank_delay_support; - enum sdw_p15_behave p15_behave; bool lane_control_support; + enum sdw_p15_behave p15_behave; u32 master_count; u32 source_ports; u32 sink_ports; - struct sdw_dp0_prop *dp0_prop; - struct sdw_dpn_prop *src_dpn_prop; - struct sdw_dpn_prop *sink_dpn_prop; - u8 scp_int1_mask; u32 quirks; + u8 scp_int1_mask; bool clock_reg_supported; bool use_domain_irq; }; |