diff options
| author |   Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2024-12-14 00:14:17 +0200 |
|---|---|---|
| committer |   Abhinav Kumar <quic_abhinavk@quicinc.com> | 2025-02-15 11:46:42 -0800 |
| commit | 2f69e54584475ac85ea0e3407c9198ac7c6ea8ad (patch) | |
| tree | c2e4ceab6913e5c3acf0dfbdd1c40268fe612b84 | |
| parent | drm/msm: Avoid rounding up to one jiffy (diff) | |
| download | wireguard-linux-2f69e54584475ac85ea0e3407c9198ac7c6ea8ad.tar.xz wireguard-linux-2f69e54584475ac85ea0e3407c9198ac7c6ea8ad.zip | |
drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450
The SM8450 and later chips have DPU_MDP_PERIPH_0_REMOVED feature bit
set, which means that those platforms have dropped some of the
registers, including the WD TIMER-related ones. Stop providing the
callback to program WD timer on those platforms.
Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/628874/
Link: https://lore.kernel.org/r/20241214-dpu-drop-features-v1-1-988f0662cb7e@linaro.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index ad19330de61a..562a3f4c5238 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, if (cap & BIT(DPU_MDP_VSYNC_SEL)) ops->setup_vsync_source = dpu_hw_setup_vsync_sel; - else + else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) ops->setup_vsync_source = dpu_hw_setup_wd_timer; ops->get_safe_status = dpu_hw_get_safe_status; |