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| author |   Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2021-04-21 17:02:20 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-04-27 09:08:50 +0200 |
| commit | 366db3ac3cdf97e90695282b959c75d5ea58cf00 (patch) | |
| tree | 530b4cdb91f7c60556ef1a51d0aaee95f0e4ceaf | |
| parent | arm64: dts: renesas: ulcb: Add cpu-supply property to a57_0 node (diff) | |
| download | wireguard-linux-366db3ac3cdf97e90695282b959c75d5ea58cf00.tar.xz wireguard-linux-366db3ac3cdf97e90695282b959c75d5ea58cf00.zip | |
arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Fix CSI40 ports
Fix the DTS schema by explicitly stating that the input is port@0. This
fixes a schema validation error but has no runtime effect as the default
port number is 0 if not specified.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20210421150221.3202955-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts index e7b4a929bb17..2e3d1981cac4 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts @@ -33,7 +33,7 @@ status = "okay"; ports { - port { + port@0 { csi40_in: endpoint { clock-lanes = <0>; data-lanes = <1 2>; |