diff options
| author |   Marek Vasut <marek.vasut+renesas@mailbox.org> | 2025-02-09 19:05:05 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-21 16:23:01 +0100 |
| commit | 399f14ff6625cbfb666c4372a469714f840f7df3 (patch) | |
| tree | 2c7dd4107f8dae0d85dacd32a25a589146bfb721 | |
| parent | ARM: dts: renesas: rcar-gen2: Add boot phase tags (diff) | |
| download | wireguard-linux-399f14ff6625cbfb666c4372a469714f840f7df3.tar.xz wireguard-linux-399f14ff6625cbfb666c4372a469714f840f7df3.zip | |
arm64: dts: renesas: rcar: Add boot phase tags
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT. Add bootph-all for all nodes that are used in the
bootloader on Renesas R-Car SoCs.
All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.
Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
25 files changed, 104 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 375a56b20f26..a10584150571 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -544,6 +544,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 05712cd96d28..380b857fd273 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -695,6 +695,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index ab8283656660..4f38b01ae18d 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -786,6 +786,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 96f3b5fe7e92..6ee9cdeb5a3a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -292,6 +292,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -299,6 +300,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -347,6 +349,7 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -485,6 +488,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7795"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -565,11 +569,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7795-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -3398,6 +3404,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index ee80f52dc7cf..a323ac47ca70 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -264,6 +264,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7796-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2996,6 +3003,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 3b9066043a71..49f6d31c5903 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -264,6 +264,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77961"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77961-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2817,6 +2824,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 557bdf8fab17..136a22ca50b7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -143,6 +143,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -150,6 +151,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -182,6 +184,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -320,6 +324,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77965"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -400,11 +405,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77965-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2828,6 +2835,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 32f07aa27316..8b594e9e9dc1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -409,6 +409,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 118e77f4477e..445f5dd7c983 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -296,6 +296,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 38145fd6acf0..01744496805c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -60,6 +60,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -67,6 +68,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -91,6 +93,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -200,6 +203,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77970"; reg = <0 0xe6060000 0 0x504>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -280,11 +284,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77970-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1196,6 +1202,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index b409a8d1737e..c2692d6fd00d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -282,6 +282,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 55a6c622f873..f7e506ad7a21 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -80,6 +80,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -87,6 +88,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -120,6 +122,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -229,6 +232,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77980"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -309,11 +313,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77980-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1579,6 +1585,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 50fbf7251665..6b8742045836 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -122,6 +122,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -153,6 +154,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -276,6 +279,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; i2c_dvfs: i2c@e60b0000 { @@ -372,11 +376,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77990-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2121,6 +2127,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 5f0828a4675b..b66cd7c90d53 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -65,6 +65,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -86,6 +87,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -209,6 +212,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77995"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -289,11 +293,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77995-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1448,6 +1454,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index e8c8fca48b69..0916fd57d1f1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -348,6 +348,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 905285b83f0c..f1613bfd1632 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -47,6 +47,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -54,6 +55,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a76 { @@ -71,6 +73,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -93,6 +97,7 @@ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6058180 { @@ -331,11 +336,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779a0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2973,6 +2980,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index e03baefb6a98..1781bb79a619 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -101,6 +101,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index fdc466b84d51..b496495c59a6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -253,6 +253,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -260,6 +261,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -296,6 +298,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -315,6 +319,7 @@ compatible = "renesas,pfc-r8a779f0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -463,11 +468,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779f0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1283,6 +1290,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index df652e7b85c9..67b18f2bffbd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -68,6 +68,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 550e7dabd1da..1760720b7128 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -166,6 +166,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -173,6 +174,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -215,6 +217,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -237,6 +241,7 @@ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, <0 0xe6068000 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -452,11 +457,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779g0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2496,6 +2503,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 99bbb8a1b7b5..4d890e0617af 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -361,6 +361,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 196b433bf82c..8524a1e7205e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -138,6 +138,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr-clk { @@ -145,6 +146,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -180,6 +182,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -201,6 +205,7 @@ <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -401,11 +406,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779h0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2158,6 +2165,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 06c7e9746304..68971c870d17 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -940,6 +940,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 0c58d816c375..fcab957b54f7 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -448,6 +448,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi index f24814d7c924..b4024e85ae5a 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -201,6 +201,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; |