diff options
| author |   Sander Vanheule <sander@svanheule.net> | 2025-01-19 19:34:16 +0100 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2025-02-21 15:09:51 +0100 |
| commit | 3b0f24d79530c4d1692ba43aa4dc9d30866fc06a (patch) | |
| tree | f8c22efa934272f019afedfee0be71ebf91a281f | |
| parent | MIPS: mobileye: dts: eyeq6h: Enable cluster support (diff) | |
| download | wireguard-linux-3b0f24d79530c4d1692ba43aa4dc9d30866fc06a.tar.xz wireguard-linux-3b0f24d79530c4d1692ba43aa4dc9d30866fc06a.zip | |
mips: dts: realtek: Decouple RTL930x base DTSI
The RTL930x SoC series is sufficiently different to warrant its own base
dtsi. This ensures no properties need to be deleted or overwritten, and
prevents accidental inclusions of updates from rtl83xx.dtsi.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> # For RTL9302C
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to '')
| -rw-r--r-- | arch/mips/boot/dts/realtek/rtl930x.dtsi | 133 |
1 files changed, 83 insertions, 50 deletions
diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi index 17577457d159..67261d6fcaa7 100644 --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -1,10 +1,23 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause -#include "rtl83xx.dtsi" - / { compatible = "realtek,rtl9302-soc"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpuintc: cpuintc { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -58,64 +71,84 @@ status = "disabled"; }; }; -}; -&soc { - ranges = <0x0 0x18000000 0x20000>; + soc: soc@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x20000>; - intc: interrupt-controller@3000 { - compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; - reg = <0x3000 0x18>, <0x3018 0x18>; - interrupt-controller; - #interrupt-cells = <1>; + intc: interrupt-controller@3000 { + compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; + reg = <0x3000 0x18>, <0x3018 0x18>; + interrupt-controller; + #interrupt-cells = <1>; - interrupt-parent = <&cpuintc>; - interrupts = <2>, <3>, <4>, <5>, <6>, <7>; - }; + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>, <7>; + }; - spi0: spi@1200 { - compatible = "realtek,rtl8380-spi"; - reg = <0x1200 0x100>; + spi0: spi@1200 { + compatible = "realtek,rtl8380-spi"; + reg = <0x1200 0x100>; - #address-cells = <1>; - #size-cells = <0>; - }; + #address-cells = <1>; + #size-cells = <0>; + }; - timer0: timer@3200 { - compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; - reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, - <0x3230 0x10>, <0x3240 0x10>; + timer0: timer@3200 { + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; - interrupt-parent = <&intc>; - interrupts = <7>, <8>, <9>, <10>, <11>; - clocks = <&lx_clk>; - }; + interrupt-parent = <&intc>; + interrupts = <7>, <8>, <9>, <10>, <11>; + clocks = <&lx_clk>; + }; - snand: spi@1a400 { - compatible = "realtek,rtl9301-snand"; - reg = <0x1a400 0x44>; - interrupt-parent = <&intc>; - interrupts = <19>; - clocks = <&lx_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; + snand: spi@1a400 { + compatible = "realtek,rtl9301-snand"; + reg = <0x1a400 0x44>; + interrupt-parent = <&intc>; + interrupts = <19>; + clocks = <&lx_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; -&uart0 { - /delete-property/ clock-frequency; - clocks = <&lx_clk>; + uart0: serial@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x100>; - interrupt-parent = <&intc>; - interrupts = <30>; -}; + clocks = <&lx_clk>; -&uart1 { - /delete-property/ clock-frequency; - clocks = <&lx_clk>; + interrupt-parent = <&intc>; + interrupts = <30>; - interrupt-parent = <&intc>; - interrupts = <31>; -}; + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + status = "disabled"; + }; + + uart1: serial@2100 { + compatible = "ns16550a"; + reg = <0x2100 0x100>; + + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <31>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + }; +}; |