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| author |   Thomas Bonnefille <thomas.bonnefille@bootlin.com> | 2024-08-29 14:31:52 +0200 |
|---|---|---|
| committer |   Inochi Amaoto <inochiama@gmail.com> | 2024-10-22 08:39:53 +0800 |
| commit | 45a544a62ef7cac9ecc69585a90da72ca68af898 (patch) | |
| tree | f4e03c1989d0f83875571f614471b17b42bd3762 | |
| parent | riscv: dts: sophgo: Add LicheeRV Nano board device tree (diff) | |
| download | wireguard-linux-45a544a62ef7cac9ecc69585a90da72ca68af898.tar.xz wireguard-linux-45a544a62ef7cac9ecc69585a90da72ca68af898.zip | |
riscv: dts: sophgo: Add SARADC description for Sophgo CV1800B
Add SARADC node for the Successive Approximation Analog to
Digital Converter used in Sophgo CV1800B SoC.
This patch only adds the active domain controller.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20240829-sg2002-adc-v5-3-aacb381e869b@bootlin.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index b724fb6d9689..bef89979df78 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -133,6 +133,28 @@ }; }; + saradc: adc@30f0000 { + compatible = "sophgo,cv1800b-saradc"; + reg = <0x030f0000 0x1000>; + clocks = <&clk CLK_SARADC>; + interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + channel@0 { + reg = <0>; + }; + + channel@1 { + reg = <1>; + }; + + channel@2 { + reg = <2>; + }; + }; + i2c0: i2c@4000000 { compatible = "snps,designware-i2c"; reg = <0x04000000 0x10000>; |