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| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2025-01-23 18:05:06 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-21 16:23:01 +0100 |
| commit | 495af7647560c2b3a9c3107ea81dfd7d7c8a38c0 (patch) | |
| tree | 378625f4e2a270e1311bb9dee69d735a4d6a4963 | |
| parent | arm64: dts: renesas: r8a779f0: Disable rswitch ports by default (diff) | |
| download | wireguard-linux-495af7647560c2b3a9c3107ea81dfd7d7c8a38c0.tar.xz wireguard-linux-495af7647560c2b3a9c3107ea81dfd7d7c8a38c0.zip | |
arm64: dts: renesas: r9a08g045: Enable SYS node
Enable the System Controller. It is needed for SoC identification.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250123170508.13578-8-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index a9b98db9ef95..d1e228b439df 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -443,7 +443,6 @@ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; - status = "disabled"; }; pinctrl: pinctrl@11030000 { |