diff options
| author |   Vlad Dogaru <vdogaru@nvidia.com> | 2025-03-11 00:01:40 +0200 |
|---|---|---|
| committer |   Paolo Abeni <pabeni@redhat.com> | 2025-03-13 13:11:14 +0100 |
| commit | 521992337f67f71ce4436b98bc32563ddb1a5ce3 (patch) | |
| tree | 9ceea2f88280fcf601b6d313b98c4cb9f2161032 | |
| parent | net/mlx5: DR, use the right action structs for STEv3 (diff) | |
| download | wireguard-linux-521992337f67f71ce4436b98bc32563ddb1a5ce3.tar.xz wireguard-linux-521992337f67f71ce4436b98bc32563ddb1a5ce3.zip | |
net/mlx5: HWS, Rightsize bwc matcher priority
The bwc layer was clamping the matcher priority from 32 bits to 16 bits.
This didn't show up until a matcher was resized, since the initial
native matcher was created using the correct 32 bit value.
The fix also reorders fields to avoid some padding.
Fixes: 2111bb970c78 ("net/mlx5: HWS, added backward-compatible API handling")
Signed-off-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1741644104-97767-3-git-send-email-tariqt@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h index f9f569131dde..47f7ed141553 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.h @@ -24,8 +24,8 @@ struct mlx5hws_bwc_matcher { struct mlx5hws_matcher *matcher; struct mlx5hws_match_template *mt; struct mlx5hws_action_template *at[MLX5HWS_BWC_MATCHER_ATTACH_AT_NUM]; + u32 priority; u8 num_of_at; - u16 priority; u8 size_log; atomic_t num_of_rules; struct list_head *rules; |