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| author |   Jisheng Zhang <jszhang@kernel.org> | 2024-04-29 08:13:10 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2024-04-30 22:04:16 +0100 |
| commit | 5e7922abddd4aab1dd604aa3fc7905d2c638c92b (patch) | |
| tree | 891d1fc83a253e9af1feb3184960f470f9522cb3 | |
| parent | riscv: dts: starfive: visionfive 2: Remove non-existing I2S hardware (diff) | |
| download | wireguard-linux-5e7922abddd4aab1dd604aa3fc7905d2c638c92b.tar.xz wireguard-linux-5e7922abddd4aab1dd604aa3fc7905d2c638c92b.zip | |
riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsi
Add the 'cpus' label so that we can reference it in board dts files.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 9a2e9583af88..7de0732b8eab 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -13,7 +13,7 @@ #address-cells = <2>; #size-cells = <2>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4a5708f7fcf7..18047195c600 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -15,7 +15,7 @@ #address-cells = <2>; #size-cells = <2>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; |