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| author |   Johan Hovold <johan+linaro@kernel.org> | 2024-07-22 11:42:45 +0200 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2024-07-30 08:49:15 -0500 |
| commit | 6e3902c499544291ac4fd1a1bb69f2e9037a0e86 (patch) | |
| tree | f8c40a056700bd2a56d2df00dcd7f9098f0c5e95 | |
| parent | arm64: dts: qcom: x1e80100: add missing PCIe minimum OPP (diff) | |
| download | wireguard-linux-6e3902c499544291ac4fd1a1bb69f2e9037a0e86.tar.xz wireguard-linux-6e3902c499544291ac4fd1a1bb69f2e9037a0e86.zip | |
arm64: dts: qcom: x1e80100-crd: fix up PCIe6a pinctrl node
The PCIe6a pinctrl node appears to have been copied from the sc8280xp
CRD dts, which has the NVMe on pcie2a and uses some funny indentation.
Fix up the node name to match the x1e80100 use and label and use only
tabs for indentation.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240722094249.26471-5-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index dabc9362c72c..85e32101a471 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -931,7 +931,7 @@ bias-disable; }; - pcie6a_default: pcie2a-default-state { + pcie6a_default: pcie6a-default-state { clkreq-n-pins { pins = "gpio153"; function = "pcie6a_clk"; @@ -947,11 +947,11 @@ }; wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; tpad_default: tpad-default-state { |