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| author |   Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> | 2024-12-20 10:14:40 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-01-07 17:00:56 +0100 |
| commit | 7088d2d7e9a58a972d8c07b4d74837f3c524f2f4 (patch) | |
| tree | 26b9c6825d76a6067416fbb90ed1d73255fac84b | |
| parent | clk: renesas: r8a779g0: Add FCPVX clocks (diff) | |
| download | wireguard-linux-7088d2d7e9a58a972d8c07b4d74837f3c524f2f4.tar.xz wireguard-linux-7088d2d7e9a58a972d8c07b4d74837f3c524f2f4.zip | |
clk: renesas: r8a779g0: Add VSPX clocks
Add the VSPX modules clock for Renesas R-Car V4H (R8A779G0) SoC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-3-7dc1812585ad@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index f41e7382a5e6..d45571096b96 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("pfc2", 917, R8A779G0_CLK_CP), DEF_MOD("pfc3", 918, R8A779G0_CLK_CP), DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M), + DEF_MOD("vspx0", 1028, R8A779G0_CLK_S0D1_VIO), + DEF_MOD("vspx1", 1029, R8A779G0_CLK_S0D1_VIO), DEF_MOD("fcpvx0", 1100, R8A779G0_CLK_S0D1_VIO), DEF_MOD("fcpvx1", 1101, R8A779G0_CLK_S0D1_VIO), DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC), |