diff options
| author |   Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2023-03-27 09:42:17 +0300 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2023-04-03 11:36:49 +0300 |
| commit | 95d939bb97ff9be101ae4ceeb322535589da2190 (patch) | |
| tree | b871fdc447b1dd945e5ae4c2dc28223fa3c1691d | |
| parent | drm/i915/huc: Cancel HuC delayed load timer on reset. (diff) | |
| download | wireguard-linux-95d939bb97ff9be101ae4ceeb322535589da2190.tar.xz wireguard-linux-95d939bb97ff9be101ae4ceeb322535589da2190.zip | |
drm/i915: Use compressed bpp when calculating m/n value for DP MST DSC
For obvious reasons, we use compressed bpp instead of pipe bpp for
DSC DP SST case. Lets be consistent and use compressed bpp instead of
pipe bpp, also in DP MST DSC case.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Fixes: d51f25eb479a ("drm/i915: Add DSC support to MST path")
Link: https://patchwork.freedesktop.org/patch/msgid/20230327064217.24033-1-stanislav.lisovskiy@intel.com
(cherry picked from commit ea1deabc6f11575eb3375b454457eaa3c9837abc)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 2106b3de225a..7c9b328bc2d7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -232,7 +232,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, return slots; } - intel_link_compute_m_n(crtc_state->pipe_bpp, + intel_link_compute_m_n(crtc_state->dsc.compressed_bpp, crtc_state->lane_count, adjusted_mode->crtc_clock, crtc_state->port_clock, |