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| author |   Arnd Bergmann <arnd@arndb.de> | 2025-03-06 16:32:17 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-03-06 16:32:18 +0100 |
| commit | b86114f680f264b741b07d99a1175f0e2d4d20f0 (patch) | |
| tree | a075a7f43676b795a61cbe37c5ffe53eaa9b0f14 | |
| parent | Merge tag 'arm-soc/for-6.14/devicetree-fixes' of https://github.com/Broadcom/stblinux into arm/fixes (diff) | |
| parent | arm64: dts: bcm2712: PL011 UARTs are actually r1p5 (diff) | |
| download | wireguard-linux-b86114f680f264b741b07d99a1175f0e2d4d20f0.tar.xz wireguard-linux-b86114f680f264b741b07d99a1175f0e2d4d20f0.zip | |
Merge tag 'arm-soc/for-6.14/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux into arm/fixes
This pull request contains Broadcom ARM64-based SoCs Device Tree fixes
for 6.14, please pull the following:
- Phil fixes the Raspberry Pi 5 PL011 UART primecell ID to indicate it
is r1p5 and thus has a 32-byte FIFO
* tag 'arm-soc/for-6.14/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux:
arm64: dts: bcm2712: PL011 UARTs are actually r1p5
Link: https://lore.kernel.org/r/20250225194041.1063762-2-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 689c82b7f596..9e610a89a337 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -227,7 +227,7 @@ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_uart>, <&clk_vpu>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; |