diff options
| author |   Christophe JAILLET <christophe.jaillet@wanadoo.fr> | 2023-07-07 22:06:27 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-07-11 09:58:27 +0200 |
| commit | bbceb13ce2c7b084bbbf2463ac8ac2b1f2bd2949 (patch) | |
| tree | 838e4b509253a7aca9044fc5e68fd7e801550412 | |
| parent | clk: renesas: r9a09g011: Add CSI related clocks (diff) | |
| download | wireguard-linux-bbceb13ce2c7b084bbbf2463ac8ac2b1f2bd2949.tar.xz wireguard-linux-bbceb13ce2c7b084bbbf2463ac8ac2b1f2bd2949.zip | |
clk: renesas: rzg2l: Simplify .determine_rate()
rzg2l_cpg_sd_clk_mux_determine_rate() is the same as
__clk_mux_determine_rate_closest(), so use the latter to save some LoC.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/fed02e0325275df84e2d76f8c481e40e7023cbd9.1688760372.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index bc623515ad84..255920c064d9 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -182,12 +182,6 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core, return clk_hw->clk; } -static int rzg2l_cpg_sd_clk_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST); -} - static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct sd_hw_data *hwdata = to_sd_hw_data(hw); @@ -250,7 +244,7 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) } static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = { - .determine_rate = rzg2l_cpg_sd_clk_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate_closest, .set_parent = rzg2l_cpg_sd_clk_mux_set_parent, .get_parent = rzg2l_cpg_sd_clk_mux_get_parent, }; |