diff options
| author |   Minda Chen <minda.chen@starfivetech.com> | 2023-07-26 03:06:08 -0700 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-07-26 17:13:37 +0100 |
| commit | c2a10081c0335c9cd60a11d69562d06ccf0a0a02 (patch) | |
| tree | 917d614c77f3fd081ac92475824c46bbf1bc1635 | |
| parent | riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zones (diff) | |
| download | wireguard-linux-c2a10081c0335c9cd60a11d69562d06ccf0a0a02.tar.xz wireguard-linux-c2a10081c0335c9cd60a11d69562d06ccf0a0a02.zip | |
riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 90aabeac7b51..dbc1243a0e75 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -446,6 +446,27 @@ status = "disabled"; }; + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x0 0x10200000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names = "125m", "app_125m"; + #phy-cells = <0>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + stgcrg: clock-controller@10230000 { compatible = "starfive,jh7110-stgcrg"; reg = <0x0 0x10230000 0x0 0x10000>; |