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| author |   Claudiu Beznea <claudiu.beznea@microchip.com> | 2018-12-12 16:31:11 +0000 |
|---|---|---|
| committer |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2019-01-08 19:12:30 +0100 |
| commit | c2dfab7e40095b29668a4022a5558549e544e3cd (patch) | |
| tree | 21259e80541be6d48403e788078c05ec76d61a07 | |
| parent | ARM: dts: at91: at91-sama5d27_som1: add QSPI1 + SPI NOR memory nodes (diff) | |
| download | wireguard-linux-c2dfab7e40095b29668a4022a5558549e544e3cd.tar.xz wireguard-linux-c2dfab7e40095b29668a4022a5558549e544e3cd.zip | |
ARM: dts: at91: at91-sama5d27_som1_ek: enable qspi1 memory
Enable qspi1.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 4a258867ddf1..a48180555ef5 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -109,6 +109,10 @@ status = "okay"; }; + qspi1: spi@f0024000 { + status = "okay"; + }; + spi0: spi@f8000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; |