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author | 2024-08-18 19:28:42 +0200 | |
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committer | 2024-09-04 14:32:02 +0000 | |
commit | c62a0b8fe8bfbaa78efe5de7b30a9d0d225be1ab (patch) | |
tree | 8560678bcec15d4224635a7066ee3e78d30dde9a | |
parent | dt-bindings: PCI: hisilicon,kirin-pcie: Add top-level constraints (diff) | |
download | wireguard-linux-c62a0b8fe8bfbaa78efe5de7b30a9d0d225be1ab.tar.xz wireguard-linux-c62a0b8fe8bfbaa78efe5de7b30a9d0d225be1ab.zip |
dt-bindings: PCI: renesas,pci-rcar-gen2: Add top-level constraints
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".
Add missing top-level constraints for clocks and clock-names.
Link: https://lore.kernel.org/linux-pci/20240818172843.121787-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Diffstat (limited to '')
-rw-r--r-- | Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml index b288cdb1ec70..065b7508d288 100644 --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -42,9 +42,13 @@ properties: interrupts: maxItems: 1 - clocks: true + clocks: + minItems: 1 + maxItems: 3 - clock-names: true + clock-names: + minItems: 1 + maxItems: 3 resets: maxItems: 1 |