diff options
| author |   Arnd Bergmann <arnd@arndb.de> | 2025-01-16 15:30:27 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2025-01-16 15:30:27 +0100 |
| commit | d1181e342bff46837d93ca6534e0c8117856d92d (patch) | |
| tree | a13d0679b26f2c5b2dcf664f7b89c9bf90fbd571 | |
| parent | Merge tag 'v6.14-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt (diff) | |
| parent | ARM: dts: qcom: sdx55: Disable USB U1/U2 entry (diff) | |
| download | wireguard-linux-d1181e342bff46837d93ca6534e0c8117856d92d.tar.xz wireguard-linux-d1181e342bff46837d93ca6534e0c8117856d92d.zip | |
Merge tag 'qcom-arm32-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm32 DeviceTree updates for v6.14
Describe the interconnect paths for PCIe EP controllers on SDX55 and
SDX65. Disable USB U1/U2 entry to improve USB stability on the same.
* tag 'qcom-arm32-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: sdx55: Disable USB U1/U2 entry
ARM: dts: qcom: sdx65: Disable USB U1/U2 entry
ARM: dts: qcom: sdx55: Add CPU PCIe EP interconnect path
ARM: dts: qcom: sdx65: Add PCIe EP interconnect path
Link: https://lore.kernel.org/r/20250111171126.369502-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 7 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 6 |
2 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index d0f6120b665d..39530eb580ea 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -427,8 +427,9 @@ interrupt-names = "global", "doorbell"; - interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "pcie-mem"; + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; @@ -613,6 +614,8 @@ iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 3bc67bb8c1eb..6b23ee676c9e 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -335,6 +335,10 @@ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "global", "doorbell"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; @@ -526,6 +530,8 @@ iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; |