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authorChen-Yu Tsai <wens@csie.org>2025-01-04 20:16:32 +0800
committerChen-Yu Tsai <wens@csie.org>2025-01-04 20:16:32 +0800
commitdbfda1fdf2f8232ea778b25025e8b8def7d2d3af (patch)
tree91a2f813bd543b1507437ac1cb451c08f3cf3600
parentarm64: dts: allwinner: h313: enable DVFS for Tanix TX1 (diff)
parentdt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI (diff)
downloadwireguard-linux-dbfda1fdf2f8232ea778b25025e8b8def7d2d3af.tar.xz
wireguard-linux-dbfda1fdf2f8232ea778b25025e8b8def7d2d3af.zip
Merge branch 'sunxi/shared-clk-ids-for-6.14' into sunxi/dt-for-6.14
Diffstat (limited to '')
-rw-r--r--include/dt-bindings/clock/sun50i-a64-ccu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
index 175892189e9d..4f220ea7a23c 100644
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -44,7 +44,9 @@
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
#define CLK_PLL_VIDEO0 7
+#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_PERIPH0 11
+#define CLK_PLL_MIPI 17
#define CLK_CPUX 21
#define CLK_BUS_MIPI_DSI 28