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| author |   Dmitry Osipenko <digetx@gmail.com> | 2019-10-25 01:14:08 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-10-29 20:29:16 +0100 |
| commit | dc6fdedf77d151278de56d126759bccc231499b1 (patch) | |
| tree | 2982e3b2314760bd4d859d300934f4bcf0b021f6 | |
| parent | ARM: tegra: Add External Memory Controller node on Tegra30 (diff) | |
| download | wireguard-linux-dc6fdedf77d151278de56d126759bccc231499b1.tar.xz wireguard-linux-dc6fdedf77d151278de56d126759bccc231499b1.zip | |
ARM: tegra: Add Tegra20 CPU clock
All CPU cores share the same CPU clock.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 8c942e60703e..9c58e7fcf5c0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -851,12 +851,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; }; |