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authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>2025-02-13 12:20:07 +0100
committerAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>2025-03-06 10:53:06 +0100
commitdf514c118e2fccb8808598da4dd1b17509fe8780 (patch)
treedef9b4fd807d079eaf5699ed648adc38efa52904
parentarm64: dts: mediatek: mt8195: Add base display controller graph (diff)
downloadwireguard-linux-df514c118e2fccb8808598da4dd1b17509fe8780.tar.xz
wireguard-linux-df514c118e2fccb8808598da4dd1b17509fe8780.zip
arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays
The base SoC devicetree now defines a display controller graph: connect the board specific outputs (eDP internal display, DP external display) to fully migrate Cherry and make it finally possible to make Chromebooks and other board types to coexist without per-board driver modifications. Link: https://lore.kernel.org/r/20250213112008.56394-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to '')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi184
1 files changed, 177 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 5056e07399e2..e70599807bb1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -297,12 +297,29 @@
cpu-supply = <&mt6315_6_vbuck1>;
};
+&dither0_out {
+ remote-endpoint = <&dsc0_in>;
+};
+
&dp_intf0 {
status = "okay";
- port {
- dp_intf0_out: endpoint {
- remote-endpoint = <&edp_in>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_intf0_in: endpoint {
+ remote-endpoint = <&merge0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_intf0_out: endpoint {
+ remote-endpoint = <&edp_in>;
+ };
};
};
};
@@ -310,9 +327,51 @@
&dp_intf1 {
status = "okay";
- port {
- dp_intf1_out: endpoint {
- remote-endpoint = <&dptx_in>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ dp_intf1_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&merge5_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dp_intf1_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dptx_in>;
+ };
+ };
+ };
+};
+
+&dsc0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsc0_in: endpoint {
+ remote-endpoint = <&dither0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsc0_out: endpoint {
+ remote-endpoint = <&merge0_in>;
+ };
};
};
};
@@ -357,6 +416,35 @@
};
};
+&ethdr0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ ethdr0_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vdosys1_ep_ext>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ ethdr0_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&merge5_in>;
+ };
+ };
+ };
+};
+
&disp_pwm0 {
status = "okay";
@@ -376,8 +464,12 @@
#size-cells = <0>;
port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
- dptx_in: endpoint {
+
+ dptx_in: endpoint@1 {
+ reg = <1>;
remote-endpoint = <&dp_intf1_out>;
};
};
@@ -511,6 +603,56 @@
};
};
+&merge0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge0_in: endpoint {
+ remote-endpoint = <&dsc0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ merge0_out: endpoint {
+ remote-endpoint = <&dp_intf0_in>;
+ };
+ };
+ };
+};
+
+&merge5 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ merge5_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ethdr0_out>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ merge5_out: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dp_intf1_in>;
+ };
+ };
+ };
+};
+
&mfg0 {
domain-supply = <&mt6315_7_vbuck1>;
};
@@ -612,6 +754,10 @@
};
};
+&ovl0_in {
+ remote-endpoint = <&vdosys0_ep_main>;
+};
+
&pcie1 {
status = "okay";
@@ -1363,6 +1509,18 @@
status = "okay";
};
+&vdosys0 {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdosys0_ep_main: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ovl0_in>;
+ };
+ };
+};
+
/*
* For the USB Type-C ports the role and alternate modes switching is
* done by the EC so we set dr_mode to host to avoid interfering.
@@ -1385,6 +1543,18 @@
status = "okay";
};
+&vdosys1 {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdosys1_ep_ext: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ethdr0_in>;
+ };
+ };
+};
+
&xhci0 {
status = "okay";